Transistor array and manufacturing method thereof, semiconductor device and manufacturing method thereof

Abstract

The invention provides a transistor array, a manufacturing method thereof, a semiconductor device and a manufacturing method thereof. The manufacturing method of the transistor array comprises the steps: providing a wafer; etching the wafer from the first surface part of the wafer along the first direction to form a latticed etching groove and a transistor column array, wherein the transistor column array comprises a plurality of transistor columns arranged in an array, the transistor columns are arranged at grid points of the latticed groove, the first preset thickness of the transistor columns is smaller than the initial thickness of the wafer, the first direction is a wafer thickness direction, and the first surface is vertical to the first direction; depositing an insulating material in the latticed etching groove to form an insulating layer surrounding the transistor column; etching the insulating layer to expose one side wall of the transistor column; sequentially forming a gate oxide layer and a gate on the exposed side wall of the transistor column; forming a source electrode at the first end of the transistor column; and forming a drain electrode at the second end of the transistor column, wherein the first end and the second end are opposite ends of the transistor column in the first direction, and the transistor column between the source electrode and the drain electrode forms a channel region of the transistor.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, and relates to but not limited to a transistor array and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof. Background technique [0002] Transistors are widely used as switching devices or driving devices in electronic equipment. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell. [0003] In related technologies, transistors mainly include planar transistors and buried channel transistors. However, whether it is a planar transistor or a buried channel transistor, its source (Source, S) and drain (Drain, D) are located at the gate On the horizontal sides of (Gate, G), the source and drain occupy different positions under this structure, making the area of ​​the transistor larger. In addition, in the memory device, the source and drain of the transistor will be connect...

AI Technical Summary

Problems solved by technology

[0003] In related technologies, transistors mainly include planar transistors and buried channel transistors. However, whether it is a planar transistor or a buried channel transistor, its source (Source, S) and drain (Drain, D) are located at the gate On the horizontal sides of (Gate, G), the source and drain occupy different positions under this structure, making the area of ​​the transistor larger

In addition, in the memory device, the source and drain of the transistor will be connected to different structures after being formed. When the source and drain are located on the horizontal sides of the gate, it will easily lead to complicated circuit wiring inside the memory and difficult manufacturing process. Big

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