Neural network unit, convolution operation module and convolutional neural network

Abstract

The invention provides a neural network unit. The neural network unit comprises a static random access memory unit, a forward reading isolation branch and a reverse reading isolation branch, the static random access memory unit comprises a first transmission transistor and a second transmission transistor which are electrically connected in series, and a first phase inverter and a second phase inverter which are arranged oppositely and interlocked and are connected between the first transmission transistor and the second transmission transistor in parallel, and the forward reading isolation branch is connected between the first transmission transistor and the two phase inverters which are arranged oppositely and interlocked. The forward reading isolation branch is used for converting an externally input digital voltage into an analog current to be output according to the control signal stored in the static random storage unit; a reverse readout isolation branch is connected between the second transmission transistor and the two phase inverters which are oppositely interlocked, and is used for converting an externally input digital voltage into an analog current to be output according to the control signal stored by the static random access memory unit.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a neuron network unit, a convolution operation module and a convolution neural network. Background technique [0002] With the development of the big data era, artificial intelligence has become a very important subject area, and the neural network dedicated chip is an important hardware tool for the computing system to efficiently complete the neural network calculation. The traditional computing architecture adopts the von Neumann architecture that separates computing and storage. Under the trend of big data, memory bandwidth and memory power consumption in the von Neumann architecture have begun to dominate computing bandwidth and energy. A large part of the power consumption is spent on data handling of memory and computing units. Memory-oriented in-memory computing, through the combination of neural network algorithms and storage hardware architecture, greatly reduc...

AI Technical Summary

Problems solved by technology

Although different convolution kernels can be used for multiplication and addition operations when performing convolution operations on the same set of data, based on the current simple convolutional neural network algorithm, for the data of the same set of convolution windows, up to 16-20 sets of convolutions can be used. core, so for SRAM arrays, only using 16-20 column bit lines to operate is a waste of resources for the rest of the array

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