Transposition convolution and convolution accelerator chip design method based on systolic array

Abstract

The invention discloses a transpose convolution and convolution accelerator chip design method based on a systolic array, which comprises the following steps of: designing a chip accelerator array corresponding to different calculation modes and memory access modes of a transpose convolution network model and a convolution network model; and establishing a corresponding data flow strategy to map the transposed convolution model and the convolutional network model into the chip accelerator array, so that the chip acceleration performance is improved, the training process of the generative adversarial network and the convolutional neural network can be accelerated, and the image processing performance is effectively improved.

Description

technical field [0001] The invention belongs to the technical field of artificial intelligence accelerator chip design, and in particular relates to a systolic array-based transposed convolution and convolution accelerator chip design method, including processing unit design in the chip, interconnection network design, on-chip storage design and convolution / Transpose convolutional dataflow design. Background technique [0002] Currently, transposed convolution and convolution layer model methods have been widely used in various application scenarios of deep learning. Generally, convolutional layers can be used to extract useful information in the image, such as color, contour, texture and other features, and downsample the image. Convolutional layers are widely used in image recognition, machine translation and other scenarios. The transposed convolutional layer can insert valid information into the input image, that is, upsample the input image. Transposed convolutional...

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Problems solved by technology

[0004] In order to overcome the problem of "overlap-accumulation" in the transposed convolution accelerator chip and the deficiencies of existing methods, the present invention proposes a method for designing a transposed convolution and convolution accelerator chip based on a systolic array, and develops an artificial intelligence accelerator chip. The purpose is to use the appropriate data flow strategy to directly perform chip-accelerated calculations on the transposed convolution without performing "0-insertion" operations or split operations on the transposed convolution in the chip.

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