Gate-constrained silicon-controlled rectifier and manufacturing method thereof

Abstract

A gate-constrained silicon-controlled rectifier includes: a semiconductor substrate; an N well and a P well which are generated in the semiconductor substrate, wherein the N well and the P well are arranged adjacently, a first high-concentration P-type dopant is inserted into the P well at the interface of the N well and the P well, and the first high-concentration P-type dopant extends into the N well. Therefore, the design window of the physical critical dimension of the gate constraint silicon controlled rectifier is enlarged, the process control difficulty in practical application is reduced, and the method can be suitable for the anti-static protection design of an advanced CMOS process integrated circuit. The invention discloses a manufacturing method of a gate-constrained silicon-controlled rectifier. The method comprises the following steps: providing a semiconductor substrate; forming an N well and a P well in the semiconductor substrate, wherein the N well and the P well are arranged adjacently, a first high-concentration P-type dopant is inserted into the P well at the interface of the N well and the P well, and the first high-concentration P-type dopant extends into the N well. Therefore, the gate-constrained silicon-controlled rectifier with a large critical dimension design window can be manufactured.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit devices, in particular to a gate-confined silicon-controlled rectifier. [0002] The invention also relates to the technical field of semiconductor device manufacturing, in particular to a manufacturing method of a gate-confined silicon-controlled rectifier. Background technique [0003] In the field of integrated circuit anti-static protection (ESD, Electro-Static Discharge) design, the anti-static protection design window generally depends on the operating voltage and the thickness of the gate oxide layer of the internal protected circuit. The 55-nanometer low-power (55LP) process platform is the For example, the operating voltage of the core device (1.2V MOSFET) is 1.2V, and the thickness of the gate oxide layer is 26 angstroms (Å), so the anti-static protection design window of the core device (1.2V MOSFET) of the 55nm low-power process platform is usually It is betwe...

AI Technical Summary

Problems solved by technology

[0005] The problem in the prior art is that the critical dimension A / B of the gate-constrained silicon controlled rectifier has a small design window, which makes it difficult to control the critical dimension in actual manufacturing.

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