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Semiconductor structure and forming method thereof and mask

A semiconductor and channel structure technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve the problems of difficult channel and poor control ability of gate structure to channel, so as to improve electrical performance, The effect of reducing the probability of phase bridging

Pending Publication Date: 2021-12-21
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (short-channel effects, SCE) more prone to occur

Method used

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  • Semiconductor structure and forming method thereof and mask
  • Semiconductor structure and forming method thereof and mask
  • Semiconductor structure and forming method thereof and mask

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Embodiment Construction

[0013] Currently formed semiconductor structures still suffer from poor performance. The reason for the poor performance of the semiconductor structure is analyzed in combination with a method for forming the semiconductor structure.

[0014] Figure 1 to Figure 5 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] like figure 1 and figure 2 as shown, figure 2 for figure 1 In the cross-sectional view of the AA direction, the semiconductor structure is used to form a SARM device, and the SRAM includes a pull-up transistor (PU), a pull-down transistor (PD) and a pass-gate transistor (PG), the pull-up transistor is a PMOS transistor, and the pull-down transistor The sum transfer gate transistor is an NMOS transistor; the base includes two first device regions I and the second device region II adjacent between the two first device regions I, and the base includes a substrate 1, a discrete The channel ...

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Abstract

The invention discloses a semiconductor structure and a forming method thereof and a mask. The forming method comprises the steps: providing a base, wherein the base comprises a first device region and two adjacent second device regions, the base comprises a substrate and channel structures discrete on the substrate, the extension direction of the channel structures being the same as the extension direction of the junctions of the first device region and the second device regions, and the base further comprises a gate structure crossing the channel structures, the gate structure covering a part of the top wall and a part of the side walls of each channel structure; and forming a first source-drain doping layer in the channel structures at the two sides of the gate structure in the first device region. In the embodiment of the invention, the second source-drain doping layer is formed in the second device region exposed by the first shielding layer, and the second shielding layer covers the second source-drain doping layer, so that the second source-drain doping layer formed in the second device region exposed by the second shielding layer is not easy to contact with the second source-drain doping layer in the second shielding layer, the probability of bridging of the two second source-drain doped layers is reduced, and the electrical performance of the semiconductor structure is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure, a method for forming the same, and a mask. Background technique [0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET) channel length has been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The channel becomes more and more difficult, making subthreshold leakage (subthreshold leakage), the so-called short-channel eff...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L27/092H01L27/11H10B10/00
CPCH01L21/823814H01L21/823821H01L27/0924H10B10/12
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP