In-memory sparse matrix multiplication operation method, equation solving method and solver

A technology of sparse matrix and multiplication, which is applied in the field of analog circuits, can solve the problems of increased calculation errors, storage errors, waste of storage space, etc., and achieve the effects of reducing calculation errors, reducing storage space, and reducing circuit power consumption

Active Publication Date: 2021-12-31
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

This mapping method is very effective for dense matrices, but there are a large number of 0 elements in sparse matrices. There are several disadvantages in storing these 0 elements: (1) 0 is meaningless for matrix multiplication, and storing 0 elements will waste precious storage space (2) 0 will be mapped to a low conductance value during the mapping process, but as a physical quantity, conductance cannot be equal to 0. Therefore, there is an error in the storage of 0 elements, which increases the calculation error when the array performs sparse matrix multiplication

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  • In-memory sparse matrix multiplication operation method, equation solving method and solver
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  • In-memory sparse matrix multiplication operation method, equation solving method and solver

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[0045] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0046] For ease of understanding, the structural framework of the in-memory sparse equation solver is firstly introduced.

[0047] Such as figure 1 Shown is a schematic structural diagram of an in-memory sparse matrix equation solver in an embodiment of the present invention. The in-memory sparse matrix equation solver includes a digital computing module and an in-memory computing module, where...

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Abstract

The invention discloses an in-memory sparse matrix multiplication operation method, an equation solving method and a solver, and the multiplication operation method comprises the steps of compressing an original sparse matrix to form a compressed matrix, representing the elements of the compressed matrix as complements, and splitting the matrix into a binary sign bit matrix and a binary data bit matrix; respectively storing the split matrixes into a binary memory array; representing elements multiplied by the compression matrix in the original vector as complements, splitting the complements, inputting the complements into a memory array in a voltage form, multiplying the complements by conductance of a storage bit, outputting the complements in a current form, detecting the output current, and performing analog-to-digital conversion to obtain a binary numerical value; and shifting and accumulating the product result of each memory array according to a binary operation rule to obtain the product of the original sparse matrix and the original vector. Through the operation method, the storage space can be reduced, so that the power consumption of the circuit is reduced, a low conductivity value is avoided, and the calculation error is reduced.

Description

technical field [0001] The invention belongs to the field of analog circuits, and more specifically relates to an in-memory sparse matrix multiplication operation method, an equation solving method and a solver. Background technique [0002] The storage-computing integrated architecture based on various non-volatile memories is an emerging computing architecture for processing data-intensive tasks. Since the calculation process is directly carried out in the memory, the data transmission during the operation process is minimized, making The storage-computing integrated architecture has high computing energy efficiency. At present, the memory-computing integrated architecture has made remarkable achievements in the field of neuromorphic computing. Various artificial neural networks based on non-volatile memory have proved the great potential of the memory-computing integrated technology. [0003] However, limited by the array structure of the non-volatile memory and the fixe...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4063G06F17/16G06F17/11G06F7/523
CPCG11C11/4063G06F17/16G06F17/11G06F7/523Y02D10/00
Inventor 李祎李健聪任升广余颖洁缪向水
Owner HUAZHONG UNIV OF SCI & TECH
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