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A semiconductor device and a method of manufacture

A semiconductor and isolation layer technology, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc. It can solve the problems of expensive AXI systems, inability to use AOI systems and leadless semiconductor devices, etc.

Pending Publication Date: 2022-01-21
NEXPERIA BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since semiconductor device input / output (I / O) terminals are arranged on the bottom of the device, they are hidden when the device is mounted on a PCB, so it is generally not possible to use AOI systems with leadless semiconductor devices
Automated X-ray Inspection (AXI) systems can inspect solder joints, but AXI systems are expensive

Method used

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  • A semiconductor device and a method of manufacture
  • A semiconductor device and a method of manufacture
  • A semiconductor device and a method of manufacture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0039] According to an embodiment of the invention, a vertically designed device (e.g., diode, transistor, etc.) includes solderable / bondable backside metallization and solderable / bondable frontside contacts (e.g., copper-tin (CuSn) bumps), a protective layer will be coated on the sidewalls.

[0040] During coating, the device will be mounted on a carrier (eg cut foil), which prevents the rear side from being covered.

[0041] If the front side contacts are not protected during coating, they need to be reopened after coating.

[0042] Bump planarization, grinding, polishing, etching or equivalent techniques can be used for this purpose.

[0043] Embodiments of the invention are shown in image 3 middle. In this case, the device is coated with ceramic or parylene or coating. The method includes the following steps:

[0044] STEP 300: SINGULATING THE DIE

[0045] Step 302: Coating the device with ceramic, parylene, etc.

[0046] STEP 304 : Using a bump planarization tool,...

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PUM

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Abstract

The invention relates to a semiconductor device comprising a frontside and a backside, four sidewalls, a first solder / glue connection on the frontside and a second solder / glue connection on the backside. The semiconductor device connected as a chip scale package to a printed circuit board so that the first solder / glue connection and the second solder / glue connection are visible for a visual solder / glue inspection.

Description

technical field [0001] The present invention relates to semiconductor devices. The invention also relates to a method of manufacturing a semiconductor device. Background technique [0002] A known quad flat no-lead (QFN) leadframe package is shown in FIG. 1 . [0003] Package 100 includes a die pad 102 having an inner surface 104 and an outer surface 106 . Package 100 also includes a plurality of leads 110 each having an inner surface 112 , a bottom surface 114 and a side surface 116 . The die pad 102 and the leads 110 are formed by a lead frame made of a conductive material. [0004] Leads 110 are positioned around die pad 102 and form recesses at the corners of package 100 . Side surfaces of the package 100 meet the bottom surface of the package 100 . Due to the recess, a first portion of the lead 110 close to the side surface 116 of the lead 110 has a first thickness. A second portion of the lead 110 proximate the bottom surface 114 of the lead 110 has a second diff...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L21/50H01L21/66
CPCH01L23/488H01L21/50H01L22/30H01L2224/33181H01L2224/32105H01L2224/32225H01L21/561H01L24/32H01L24/33H01L2924/10253H01L2224/29101H01L2224/83801H05K3/3442H01L23/3114H05K1/0269H01L21/6836H01L2221/68327H01L2221/68372H01L23/3135Y02P70/50H01L2924/014H01L2924/00014H01L21/78H01L23/49517H01L23/49541
Inventor 哈特穆特·宾宁汉斯-于尔根·芬克斯特凡·伯格伦德韦格尼斯沃瑞·拉马林甘贾斯廷·YH·谭罗尔夫·格罗恩休斯琼普·斯托克曼斯泰吉斯·科尼科涅
Owner NEXPERIA BV