Nested general-purpose computing parallel processing architecture

Abstract

The invention is applicable to the technical field of parallel computing task processing and processors, and provides a nested general-purpose computing parallel processing architecture which comprises general computing task execution components, the general computing task execution components comprise multiple levels in a nested mode, and each level is equivalent to a plurality of general computing task execution components; the (i + 1) th-level general calculation task execution component comprises a plurality of ith-level sub general task execution components PEi, an ith-level core data exchange component Memory i and an ith-level control unit CUi. According to the invention, the parallel computing task processing efficiency is improved from two aspects of coarse granularity and fine granularity in a nested execution mode, so that the maximum utilization rate and parallelism degree of system architecture resources are achieved. The invention is suitable for all current forms of big data parallel computing task processing processes, and has flexible expansibility and transportability at the same time.

Description

technical field [0001] The invention belongs to the technical field of parallel computing task processing and processors, and in particular relates to a nested general computing parallel processing architecture. Background technique [0002] With the surge in the amount of application data in various industries in recent years, people's requirements for data processing are increasing day by day. The emergence of multi-core CPUs and multi-core GPUs has introduced a new upsurge in high-performance computing. Studies have shown that the ability of data processing Including the development of processor efficiency, storage resources, memory access technology, etc. are not as good as people's needs. Although GPGPU improves efficiency by covering up memory access through calculation, the traditional chip architecture has been basically finalized, and the problem of memory walls has not been well resolved, which also hinders the development of chip architecture and drives the chip a...

AI Technical Summary

Problems solved by technology

The PRAM architecture of shared storage and the SIMD architecture of the Internet are not suitable for today's parallel computers, because they neither include distributed storage that conforms to parallel computing orientation nor consider practical factors such as communication and synchronization, which is not conducive to the development of chip architectures. It is actually put into production, and the scale of parallel computing is so large that it is not enough to face huge data computing tasks only by using a single-layer or a few-layer computing architecture model

[0008] In terms of describing the parallel computing architecture, the traditional parallel computing model is too abstract and does not describe the detailed components in the architecture and their logical relationship. With the development of GPGPU, more general computing is carried out on the GPU. About the GPU In the multi-version architecture white paper, the internal components of the GPU architecture, the number of components, and the supported programming methods are also divided into layers. There is a prototype for the development of parallel computing processors, but there is still no detailed expression of the logic between components. Relationships and their execution models are not conducive to in-depth industry discussions on the development of their architectures

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