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Device testing device with small spacing

A technology for testing devices and devices, which is applied in the direction of measuring devices, measuring device casings, and electronic circuit testing. It can solve problems such as alignment arrangement, unsteady intervals, and poor graphics processing units as a whole, so as to prevent poor contact and reduce alignment. Tolerance, the effect of improving reliability

Pending Publication Date: 2022-02-01
AMT 株式会社
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] figure 1 It is a bottom view showing ordinary high-bandwidth memory bumps. The high-bandwidth memory 10 has countless bumps 11 with a pitch (p) of about 125-170170 μm, which is very narrow, but they are cut and separated in the cutting process, so There is a problem that the interval (s) between the center of the bumps arranged on the edge and the edge frame cannot be constant
[0006] Therefore, when the high-bandwidth memory of this structure is produced, the bumps with small size (outer diameter) and narrow pitch cannot be accurately aligned with the terminals of the tester, so it is actually not tested. Under the factory
[0007] Moreover, when these unqualified high-bandwidth memories are installed to form a graphics processing unit (GPU, Graphical Processing Unit), it will seriously cause the problem of the overall poor graphics processing unit.

Method used

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  • Device testing device with small spacing
  • Device testing device with small spacing
  • Device testing device with small spacing

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Embodiment Construction

[0037] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Those skilled in the art can realize it in various forms, but all other embodiments obtained without creative work belong to the protection scope of the present invention. Explanation The illustrations on the drawings are simplified and not shown to scale. The relative sizes and ratios of parts in the drawings are exaggerated or reduced in illustration compared with their sizes for clarity and convenience in the drawings, and arbitrary dimensions are only examples and are not limited. The same reference symbol is used on the same structure, element or component shown on two or more drawings to highlight its similar features.

[0038] figure 2 is a perspective view showing an embodiment of the present invention,...

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Abstract

The invention relates to a device testing device for singulated devices after a plurality of semiconductor chips are laminated, for example, after a device of a high bandwidth memory (HBM) with a bump with a small size and a narrow interval and comprising a plurality of signal buses is produced, an align can be accurately carried out to carry out a performance test. To this end, the device preferably comprises: a body 20; and a loading part 40 which is arranged on one side of the main body 20 and enables a device 30 to be tested to stand by, a loading separator 60, arranged on one side of the loading part 40 and used for sequentially adsorbing the devices 30 to be tested and then placing the devices 30 on the vacuum chuck 50; a vacuum chuck (50) that moves along a rail (21) and that has a vacuum hole (51) formed in each of the placement locations of the device (30) that is sucked and moved by the loading sorter (60); a loading area 70, used for placing a device 30 to be tested on the vacuum chuck 50; and a device alignment unit (80) which is provided at the upper part of the loading area (70) so as to be movable along the X-Y-[theta] axis, confirms the position of the device (30) adsorbed on the vacuum chuck (50), transmits a coordinate value to a control unit, and aligns the device (30), and a test bench (90) which moves the device (30) adsorbed on the vacuum chuck (50) along a track (21) in an aligned state for standby; a testing machine (100) which moves the vacuum chuck (50) located on the test bench (90), electrically contacts the salient points of the devices (30), and then tests the performance of the devices within a set time; an unloading area 110 in which a vacuum chuck 50 for completing the test of the device 30 in the test machine 100 is located; and an unloading separator (140) which is arranged on one side of the unloading area (110), sorts the tested devices (30) into qualified products and unqualified products after absorbing the tested devices (30) from the vacuum chuck (50), and unloads the qualified products and the unqualified products to a tray (130) of an unloading part (120).

Description

technical field [0001] The present invention relates to a singulated device testing device after a plurality of semiconductor chips are stacked, and more specifically, such as the size of the bump (bump), the pitch is narrow, and the high bandwidth memory (HBM, High Bandwidth) containing many signal buses Memory) after the device production, accurately align (align) the device test device with a fine pitch for performance testing. Background technique [0002] At present, it has become a trend for the electronics industry to manufacture light, small, high-speed, multi-functional and high-performance products at low prices. Moreover, in order to improve the performance of integrated circuits, it has been developed into three-dimensional structures such as multi-chip stacked packages. [0003] This multi-chip stacked package High Bandwidth Memory (HBM) is a high performance (RAM) interface for three-dimensional stacked Dynamic Random Access Memory (DRAM). [0004] The high-b...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R1/04
CPCG01R31/2891G01R1/0433G01R1/0458G01R1/0483G01R31/2893G01R31/2865G01R31/287G01R31/2874
Inventor 金斗喆李玩求
Owner AMT 株式会社