SPICE voltage or temperature scanning simulation bottleneck unit screening method

Abstract

The invention discloses a SPICE voltage or temperature scanning simulation bottleneck unit screening method. The method comprises the following steps: 1) screening a time sequence path data subset of STA time sequence violation from an original time sequence path data set; 2) performing SPICE simulation on each path of the time sequence path data subset, and screening out a key path set; (3) arranging elements of the key path set in a descending order; 4) obtaining a time sequence analysis object set from the key path set in which the elements are arranged in a descending order; 5) acquiring an instance unit set from the time sequence analysis object set; 6) obtaining a trend characteristic comprehensive index of Instance Cells; and (7) constructing a time sequence sensitive time sequence unit set according to the trend characteristic comprehensive index. According to the method, STA simulation and SPICE simulation are combined, time sequence units which are more sensitive along with changes of actual voltage or temperature working conditions in key paths are screened out, and the ASIC design period is effectively shortened.

Description

technical field [0001] The invention relates to the technical field of EDA simulation tools, in particular to a method for screening bottleneck units through SPICE voltage or temperature scanning simulation. Background technique [0002] Timing analysis is a key issue in the ASIC design process. In the prior art, a traditional and simple way is to perform timing checks on timing paths or timing units (Slack, Slew, and Delay, etc.) based on STA lookup table calculations. In the case of circuit function verification, timing acceptance is completed; in another way, using SPICE voltage or temperature (Voltage / Temperature, V / T) scanning simulation can further study the trend and sensitivity of circuit timing changes with V / T changes, Study the actual working performance of the entire IC design circuit. [0003] The sequential cell library required by STA is usually established based on a fixed process and fixed voltage and temperature conditions (Process, Voltage and Temperature...

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Problems solved by technology

[0003] The sequential cell library required by STA is usually established based on a fixed process and fixed voltage and temperature conditions (Process, Voltage and Temperature, PVT). Its advantage is that it can quickly complete timing analysis without external incentives. , and the coverage rate of timing path analysis can reach almost 100%, but the disadvantage is that the establishment of these cell libraries requires huge time and capital costs, and it is difficult to keep up with the needs of the development of new IC design processes

Therefore, with the continuous improvement of IC technology, the timing analysis method based on SPICE simulation can complete the high-precision solution of gate-level or transistor-level timing parameters and the effective estimation of critical path timing parameters compared with STA. The parameter update input stimulus in the netlist file can obtain device timing data that is more in line with the real situation as the V / T condition changes through SPICE simulation, but the disadvantage is that the SPICE dynamic timing simulation takes too long and consumes a lot of resources

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