SPICE voltage or temperature scanning simulation bottleneck unit screening method

A voltage and bottleneck technology, which is applied in the field of SPICE voltage or temperature scanning simulation screening bottleneck units, can solve the problems of large resource consumption, high time and capital costs, difficult to meet the needs of IC design and new process development, etc., to reduce the amount of data, The effects of eliminating differences, organizing and calculating quickly and efficiently

Pending Publication Date: 2022-02-08
北京华大九天科技股份有限公司
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  • Claims
  • Application Information

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Problems solved by technology

[0003] The sequential cell library required by STA is usually established based on a fixed process and fixed voltage and temperature conditions (Process, Voltage and Temperature, PVT). Its advantage is that it can quickly complete timing analysis without external incentives. , and the coverage rate of timing path analysis can reach almost 100%, but the disadvantage is that the establishment of these cell libraries requires huge time and capital costs, and it is difficult to keep up with the needs of the development of new IC design processes
Therefore, with the

Method used

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  • SPICE voltage or temperature scanning simulation bottleneck unit screening method
  • SPICE voltage or temperature scanning simulation bottleneck unit screening method
  • SPICE voltage or temperature scanning simulation bottleneck unit screening method

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Embodiment 1

[0061] figure 1 For the method flowchart of screening bottleneck unit according to SPICE voltage of the present invention or temperature scanning simulation, will refer to below figure 1 , the SPICE voltage or temperature scanning simulation method for screening bottleneck units of the present invention is described in detail.

[0062] First, in step 101, the STA is used to filter out the timing path datasets with STA timing violations from the original timing path dataset.

[0063] In the embodiment of the present invention, taking advantage of the advantages of fast calculation speed and high path coverage of STA, a subset Q is preliminarily screened in the original time series path data set U, so that each element path(i) in Q satisfies the following conditions :

[0064]

[0065] Among them, Slack is the timing margin calculated by Setup or Hold timing check, Indicates the slack value calculated by the STA method for the critical path, T slack Indicates an empirica...

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Abstract

The invention discloses a SPICE voltage or temperature scanning simulation bottleneck unit screening method. The method comprises the following steps: 1) screening a time sequence path data subset of STA time sequence violation from an original time sequence path data set; 2) performing SPICE simulation on each path of the time sequence path data subset, and screening out a key path set; (3) arranging elements of the key path set in a descending order; 4) obtaining a time sequence analysis object set from the key path set in which the elements are arranged in a descending order; 5) acquiring an instance unit set from the time sequence analysis object set; 6) obtaining a trend characteristic comprehensive index of Instance Cells; and (7) constructing a time sequence sensitive time sequence unit set according to the trend characteristic comprehensive index. According to the method, STA simulation and SPICE simulation are combined, time sequence units which are more sensitive along with changes of actual voltage or temperature working conditions in key paths are screened out, and the ASIC design period is effectively shortened.

Description

technical field [0001] The invention relates to the technical field of EDA simulation tools, in particular to a method for screening bottleneck units through SPICE voltage or temperature scanning simulation. Background technique [0002] Timing analysis is a key issue in the ASIC design process. In the prior art, a traditional and simple way is to perform timing checks on timing paths or timing units (Slack, Slew, and Delay, etc.) based on STA lookup table calculations. In the case of circuit function verification, timing acceptance is completed; in another way, using SPICE voltage or temperature (Voltage / Temperature, V / T) scanning simulation can further study the trend and sensitivity of circuit timing changes with V / T changes, Study the actual working performance of the entire IC design circuit. [0003] The sequential cell library required by STA is usually established based on a fixed process and fixed voltage and temperature conditions (Process, Voltage and Temperature...

Claims

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Application Information

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IPC IPC(8): G06F30/367G06F30/3315
CPCG06F30/367G06F30/3315
Inventor 江荣贵雍晓陈彬郭超杨晓东
Owner 北京华大九天科技股份有限公司
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