High-voltage MOSFET device and manufacturing method thereof

Abstract

The invention provides a high-voltage MOSFET device and a manufacturing method thereof. The method comprises the steps: providing a substrate, forming an interface layer on the surface of the substrate, and forming a pseudo gate structure formed by superposing a polysilicon gate and a hard mask layer above the interface layer, wherein the hard mask layer comprises an upper oxide layer and a lower nitride layer; forming a plurality of gaps on the interface layer in the pseudo gate structure; forming a side wall structure on the side wall of the pseudo gate structure; forming a photoresist layer with a gap and a side wall structure pattern; taking the photoresist layer as a mask, and removing the oxide layer and a part of the photoresist layer covering the gap and the side wall structure by adopting a first dry etching process to form an ox horn-shaped structure; removing the residual photoresist layer by adopting a second dry etching process; removing the nitride layer by adopting a wet etching process; forming a contact hole etching stop layer; depositing to form an interlayer dielectric layer; and carrying out planarization by adopting a chemical mechanical grinding process. According to the invention, the height and the height consistency of the metal gate are improved, so that the electrical performance and the yield of the device are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a high-voltage MOSFET device and a manufacturing method thereof. Background technique [0002] With the continuous reduction of device size, for high voltage (HV) COMS devices with a process node below 32nm, especially below 28nm, a gate-last process is usually used to form a metal gate. In the gate-last process, the dummy gate planarization process is mainly realized by a chemical mechanical polishing (CMP) process, including steps: forming a dummy gate structure, then forming nitride sidewalls, and depositing an interlayer dielectric layer (ILD), After that, CMP is used to form a uniform dummy gate height to ensure the formation of subsequent metal gates. like figure 1 as shown, figure 1 It is a schematic diagram of the structure of the device after IDO CMP in the prior art is shown. It can be seen that after the CMP corresponding to the mark 10 is compl...

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Problems solved by technology

Depression 11 will lead to poor consistency and integrity of the subsequent metal gate, which will affect the performance of the device

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