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Semiconductor packaging structure and manufacturing method thereof

A packaging structure and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of prone to inverted pillars, functional chip cracks, and complex manufacturing processes, reducing thickness, improving Yield effect

Pending Publication Date: 2022-02-15
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the manufacturing process, it is necessary to make conductive pillars around the bridge chip to realize the connection between the substrate and the functional chip, but the process of making conductive pillars is prone to inverted pillars, and the process yield is low
Moreover, two molding process protection structures (conductive pillars, bridge chips, and functional chips) are required, and the manufacturing process is complicated
In addition, due to the thinning process performed after molding, stress is generated between functional chips and cracks are generated

Method used

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  • Semiconductor packaging structure and manufacturing method thereof
  • Semiconductor packaging structure and manufacturing method thereof
  • Semiconductor packaging structure and manufacturing method thereof

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Embodiment Construction

[0048] The specific implementation manners of the present disclosure will be described below in conjunction with the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced through the contents recorded in this specification. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. In addition, for the convenience of description, only the parts related to the related invention are shown in the drawings.

[0049] It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the specification are only used to match the content recorded in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present disclosure. There are limited conditions, so it has...

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Abstract

The invention discloses a semiconductor packaging structure and a manufacturing method thereof, a rewiring layer is directly arranged on a substrate, a groove is formed in the substrate, in addition, a functional chip and a bridging chip are combined in advance, then the bridging chip is placed in the groove, a conductive column manufacturing process and a mold packaging process are not needed, and the yield is improved. In addition, the groove provides a placement space for the bridging chip, so that the thickness of the whole structure is reduced.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, in particular to a semiconductor package structure and a manufacturing method thereof. Background technique [0002] In some cases of a System-on-Chip (SOC) structure, the thickness of the entire structure includes the thickness of the substrate, the bridge chip, and the function chip. In the manufacturing process, it is necessary to make conductive pillars around the bridge chip to realize the connection between the substrate and the functional chip. However, the process of making conductive pillars is prone to inverted pillars, and the process yield is low. Moreover, two molding processes are required to protect the structures (conductive pillars, bridge chips, and functional chips), and the manufacturing process is complicated. In addition, due to the thinning process performed after molding, stress is generated between functional chips to generate cracks. Contents of the in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/538H01L25/18H01L21/60
CPCH01L23/49838H01L23/49822H01L23/49816H01L23/5386H01L25/18H01L24/81H01L2224/0231H01L2224/02331H01L2224/02381
Inventor 吕文隆
Owner ADVANCED SEMICON ENG INC
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