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Normal-temperature ultrasonic transient solid-phase bonding method for copper indium micro-nano layer

A micro-nano, ultrasonic technology, applied in the direction of electrical solid devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as thermal stress deformation of chips and other devices, low bonding efficiency, and complicated bonding conditions

Pending Publication Date: 2022-03-01
广州华立学院
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, a temperature above 100°C is required for bonding, or heat treatment in a protective atmosphere for a period of time after bonding; therefore, the bonding efficiency is not high, and the conditions required for bonding are complicated, which will also cause heat generation in chips and other devices. The case of stress deformation

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  • Normal-temperature ultrasonic transient solid-phase bonding method for copper indium micro-nano layer
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  • Normal-temperature ultrasonic transient solid-phase bonding method for copper indium micro-nano layer

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Embodiment Construction

[0032] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0033] Such as Figure 1-Figure 11 As shown, a method for ultrasonic transient solid-phase bonding of copper indium micro-nano layers at room temperature includes an ultrasonic bonding apparatus and a loading machine. The ultrasonic bonding apparatus includes an ultrasonic horn for transmitting ultrasonic energy. The loading machine is set at the ultrasonic above the horn.

[0034] The normal-temperature ultrasonic transient solid-phase bonding method of the copper indium micro-nano layer comprises the following steps:

[0035] S1, a copper micron needle layer prepared by electrodeposition on a copper substrate;

[0036] S2. Electroplate the indium plating solution on the copper micron needle layer obtained in S1 by electroplating to obtain a substrate with a copper indium secondary micronano layer; wherein the copper indium seconda...

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Abstract

The invention provides a normal-temperature ultrasonic transient solid-phase bonding method for a copper-indium micro-nano layer. The normal-temperature ultrasonic transient solid-phase bonding method comprises the following steps: preparing a copper micron needle layer on a copper substrate through electro-deposition; s2, electroplating indium plating liquid on the copper micron needle layer obtained in the step S1 in an electroplating manner to obtain a substrate with a copper-indium secondary micro-nano layer; oppositely arranging the two substrates with the copper-indium secondary micro-nano layers on an ultrasonic bonding instrument, wherein the copper-indium secondary micro-nano layers of the two substrates form a contact area; starting an ultrasonic bonding instrument and a loading machine, and bonding the two substrates; under the condition that the ultrasonic bonding instrument provides ultrasonic energy and the loading machine provides small pressure, high-quality bonding can be obtained in a transient state; the method can be carried out in a normal-temperature air atmosphere; the method has the advantages that the bonding connection efficiency is improved, the bonding connection time is shortened, the process temperature required by bonding connection is reduced, scaling powder is not needed, the bonding residual stress is low, the process flow is simple, consumed time is short, and the green packaging concept is met.

Description

technical field [0001] The invention relates to a nano-micro connection method, in particular to a normal-temperature ultrasonic transient solid-phase bonding method of a copper indium micro-nano layer. Background technique [0002] With the development trend of miniaturization and integration of microelectronic products, stacked three-dimensional integrated packaging is the main direction of the development of electronic packaging technology. The traditional wiring interconnection technology must leave enough space for the leads, which limits the number and size of three-dimensional packaging stacks. As the number of package stacks increases, the lead density increases, exacerbating signal congestion. The thickness of the chip is getting thinner and thinner, the distance between the solder joints is getting smaller and smaller, and the high interconnection temperature seriously affects the reliability of the package. To change such an interconnection method, it is necessa...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L24/82H01L2224/82205
Inventor 肖金周艳琼翟倩程伟方湘怡
Owner 广州华立学院