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Array substrate and display panel

A technology for array substrates and display areas, applied in static indicators, nonlinear optics, instruments, etc., can solve problems such as irreversible phase transitions, achieve the effects of improving liquid crystal phase transitions and reducing wiring resistance

Pending Publication Date: 2022-03-15
CHONGQING HKC OPTOELECTRONICS TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The main purpose of this application is to provide an array substrate and a display panel. Through the hollowing process, the area of ​​the overlapping area of ​​the power signal line in the form of a hollowed out line in the frame rubber area is reduced, thereby improving the phase transition of the liquid crystal, and solving the problem of The technical problem that the liquid crystal molecules of the array substrate in the prior art are prone to irreversible phase transition

Method used

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  • Array substrate and display panel
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  • Array substrate and display panel

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] refer to figure 1 , figure 1 It is a schematic top view of the array substrate of the present application. In this embodiment, the non-display area 20 includes: a sealant area 202 surrounding the display area 10, and an overlapping area B is provided in the sealant area 202, and the overlapping Area B is used for the power signal line VSS to pass through the sealant area 202 .

[0031] It should be noted that all liquid crystal display screens need to use frame glue around the circumference. Through the frame glue curing, the thin film transistor glass substrate and the color filter glass substrate are aligned and fixed, and at the same time, the liquid crystal is sealed between the thin film transistor glass substrate and the color filter glass substrate. in the middle of a glass substrate. Frame glue curing needs to use ultraviolet light irradiation, such as figure 1 As shown, the power signal line VSS must pass through the area where the sealant is located (overla...

Embodiment 2

[0043] Based on the above embodiment, the power signal line VSS further includes a hollowed-out wiring in the overlapping area B that has been hollowed out.

[0044] It can be understood that the power signal line VSS adopts a hollow-out process technology, and the power signal line VSS is hollowed out in the overlapping area B.

[0045] The proportion of the hollow area of ​​the hollow line to the area of ​​the overlapping region B is less than or equal to a first preset value, and the proportion is greater than or equal to a second preset value, and the first preset value is greater than the second preset value.

[0046] It is easy to understand that, according to the length L of the hollowed out line, the bus width D0 of the hollowed out line, the width d1 of the hollowed out line, and the width d2 of the non-hollowed out line, the ratio of the area of ​​the hollowed out area to the area of ​​the overlapping area B can be calculated. By adjusting the The size of the line h...

Embodiment 3

[0053] Based on the above embodiment, the power signal line VSS further includes a hollowed-out wiring in the overlapping area B that has been hollowed out.

[0054] It can be understood that the power signal line VSS adopts a hollow-out process technology, and the power signal line VSS is hollowed out in the overlapping area B.

[0055] The proportion of the hollow area of ​​the hollow line to the area of ​​the overlapping region B is less than or equal to a first preset value, and the proportion is greater than or equal to a second preset value, and the first preset value is greater than the second preset value.

[0056] It is easy to understand that, according to the length L of the hollowed out line, the bus width D0 of the hollowed out line, the width d1 of the hollowed out line, and the width d2 of the non-hollowed out line, the ratio of the area of ​​the hollowed out area to the area of ​​the overlapping area B can be calculated. By adjusting the The size of the line h...

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Abstract

The invention discloses an array substrate and a display panel, and belongs to the technical field of display. The array substrate comprises a display area and a non-display area, the non-display area comprises a frame glue area surrounding the display area, an overlapping area is arranged in the frame glue area, and the overlapping area is used for a power signal line to penetrate through the frame glue area; the power supply signal line comprises a hollowed-out wire and a non-hollowed-out wire, wherein the hollowed-out wire is arranged in the overlapping area and is subjected to hollowed-out processing, and the non-hollowed-out wire is arranged outside the overlapping area. Through hollowed-out treatment, the power signal line is located in the area of the overlapping area of the frame glue area in a hollowed-out routing mode, the routing resistance is reduced, and therefore the liquid crystal phase change is improved.

Description

technical field [0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background technique [0002] When the liquid crystal display is aging at high temperature, if the thin film transistor cannot be completely turned off, the leakage current will increase, and all the leakage current will be collected on the power signal line (VSS line). Due to the large resistance and the increase of the current, the temperature of the power signal line will rise. When the temperature is higher than the phase transition temperature of the liquid crystal molecules, the liquid crystal molecules are prone to irreversible phase transitions, thereby losing display functionality. In the current product, the power signal line needs to be turned and connected to the plane. Due to space constraints, the line width of the power signal line in the turning area will suddenly narrow, and the line width will be narrowed sh...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1339G02F1/133
CPCG02F1/1339G02F1/133
Inventor 毛晗康报虹
Owner CHONGQING HKC OPTOELECTRONICS TECH CO LTD
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