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MOS device and manufacturing method thereof

A technology of MOS devices and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as affecting the turn-on voltage, achieve the effects of enhancing withstand voltage capability, improving withstand voltage performance, and reducing interface strain

Pending Publication Date: 2022-03-22
杭州富芯半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a MOS device and its manufacturing method, which is used to solve the problem in the prior art that the turn-on voltage is affected while improving the withstand voltage capability of the MOS device

Method used

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  • MOS device and manufacturing method thereof
  • MOS device and manufacturing method thereof
  • MOS device and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0073] In this implementation, a method of manufacturing a MOS device is provided, please refer to figure 2 , shown as a process flow diagram of the method, comprising the following steps:

[0074] S1: providing a substrate, the substrate is provided with a source region and a drain region arranged at intervals in a horizontal direction;

[0075] S2: forming a sandwich structure on the substrate, the sandwich structure including first SiO stacked sequentially from bottom to top 2 layer, high-K dielectric layer and the second SiO 2 layer;

[0076] S3: forming grooves in the sandwich structure, the grooves are formed from the second SiO 2 The upper surface of the layer is open and extends downwards, but does not penetrate through the sandwich structure, the groove is located between the source region and the drain region in the horizontal direction, and the source region points to the drain region In the direction of the groove, the depth at both ends of the groove is less ...

Embodiment 2

[0104] This embodiment provides a MOS device, which can be manufactured by using the method in Embodiment 1 or other suitable methods.

[0105] see Figure 11, the MOS device includes a substrate 201, a sandwich structure, a groove 207, a gate conductive layer 210, and a sidewall structure, wherein the substrate 201 is provided with a source region 202 and a drain region arranged at intervals in the horizontal direction 203; the sandwich structure is located on the substrate 201 and includes first SiO stacked sequentially from bottom to top 2 layer 204, high-K dielectric layer 205 and the second SiO 2 layer 206; the groove 207 is located in the sandwich structure, the groove 207 is formed from the second SiO 2 The upper surface of the layer 206 is open and extends downwards, but does not penetrate through the sandwich structure, the groove 207 is located between the source region 202 and the drain region 203 in the horizontal direction, and in the source region 202 Pointing...

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Abstract

The invention provides an MOS (Metal Oxide Semiconductor) device and a manufacturing method thereof, and the method comprises the following steps: providing a substrate which is internally provided with a source region and a drain region which are arranged at an interval in the horizontal direction; forming a sandwich structure on the substrate, wherein the sandwich structure comprises a first SiO2 layer, a high-K dielectric layer and a second SiO2 layer which are sequentially stacked from bottom to top; a groove is formed, the groove is opened from the upper surface of the second SiO2 layer and extends downwards into the high-K dielectric layer, the groove is located between the source region and the drain region in the horizontal direction, the depth of the two ends of the groove is smaller than the depth of the middle of the groove in the direction that the source region points to the drain region; a gate conductive layer is formed, the gate conductive layer is located on the second SiO2 layer and is filled in the groove, and the width of the gate conductive layer is larger than that of the groove; and forming a side wall structure on the side wall of the gate conductive layer. According to the invention, the voltage resistance of the device can be improved under the condition that the turn-on voltage is not influenced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and relates to a MOS device and a manufacturing method thereof. Background technique [0002] The commonly used gate oxide structures in semiconductor manufacturing technology are as follows: figure 1 As shown, it includes a substrate 101 , a source 102 , a drain 103 , a gate oxide layer 104 , a polysilicon gate 105 and spacers 106 . [0003] The threshold voltage and withstand voltage capability of MOS devices are important criteria for measuring device performance. Finding a suitable threshold voltage and improving the withstand voltage capability of devices is also an important development direction of devices at present. [0004] Basic characteristics such as threshold voltage and withstand voltage capability are closely related to conditions such as the channel length of the device and the thickness of the gate silicon oxide. It is generally desired to have a high...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/78H01L21/336
CPCH01L29/4236H01L29/42368H01L29/66477H01L29/78H01L29/66568H01L29/513H01L29/0607H01L29/401H01L29/42376
Inventor 余祺
Owner 杭州富芯半导体有限公司