Module FPGA verification method and system for chip video decoding IP

Abstract

The invention discloses a module FPGA verification method and system for a chip video decoding IP, and relates to the technical field of integrated circuit design. The method is used for verifying an IP core without an operating system, and comprises the following steps of: importing video decoding firmware of a decoding IP core into an FPGA verification platform; the verification synchronization management unit configures the number of parallel decoding verification paths of each decoding IP core and video standard parameter information of each path, and a result comparison unit on the PC is initialized; starting multi-channel communication between the result comparison unit and the video decoding firmware, and carrying out multi-channel multi-standard parallel decoding on multi-channel video streams with different video standards through the video decoding firmware for multi-channel decoding verification video streams of each decoding IP core; and transmitting the decoded frame data of each path of video stream to a result comparison unit on the PC, and comparing the decoded frame data with corresponding standard data to verify a decoding result. The chip verification period can be remarkably shortened, and the chip verification speed can be increased.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a module FPGA verification method and system for chip video decoding IP. Background technique [0002] In modern digital integrated circuit design, chip IP core verification is becoming more and more important. The verification of the video decoding IP core (also called IP or IP module) belongs to the front-end verification in the design process of the video decoding chip. The success or failure of the IP core verification directly affects the test performance of the video decoding core. At present, the verification process of the video decoding IP core can be divided into three stages: the RTL (Register-Transfer-Level) simulation verification stage of the IP core, and the FPGA (Field-Programmable Gate Array) verification stage of the IP core module And the system driver verification stage of IP core, the first two stages belong to separate module-level verific...

AI Technical Summary

Problems solved by technology

For multi-channel multi-standard video decoding and verification scenarios, the current industry practice is to set multiple sets of video decoding firmware and multiple sets of PC codes to run multiple times in time, resulting in a significant increase in the tape-out cycle of the chip and increasing the overall development of the chip product. Furthermore, due to the need to manage multiple sets of video decoding firmware, multiple sets of PC codes, and multiple sets of standard C codes, the cost of standard C codes, video decoding firmware, interaction between video decoding firmware and hardware, and PC codes is reduced. management efficiency

[0005] 2) In the verification scenario of multi-channel multi-standard decoding, a decoding IP core may cause decoding errors due to the coupling between decoding of different video standards. Moreover, multiple decoding IP cores in the chip may also decode simultaneously Parallel decoding errors may be caused by coupling. The above-mentioned problems are difficult to be found in the second stage based on the single-channel single-standard, and often need to be discovered in the third stage-the system-level verification stage of the operating system.

[0006] On the other hand, as people's requirements for chip functions are getting higher and higher, the complexity of chip design is also increasing. The traditional IP core FPGA verification system that only supports single channel and single standard is difficult to handle parallel verification of multiple decoding IP cores. And the complex mode of multi-standard parallel verification cannot meet the current chip video decoding verification requirements

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