Non-volatile memory device with peripheral on-structure cells

Abstract

A non-volatile memory device having a cell-on-periphery (COP) structure includes a first sub-memory plane and a second sub-memory plane disposed adjacent to the first sub-memory plane in a row direction. A first vertical contact region is disposed in a cell region of the first sub-memory plane and a second vertical contact region is disposed in a cell region of the second sub-memory plane. A first overhead region is disposed in the cell region of the first sub-memory plane and adjacent to the second vertical contact region in the row direction, and a second overhead region is disposed in the cell region of the second sub-memory plane and adjacent to the first vertical contact region in the row direction. A cell channel structure is disposed in a main region of the cell region.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Patent Application No. 10-2020-0132567 filed with the Korean Intellectual Property Office (KIPO) on October 14, 2020, the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] The inventive concept generally relates to a semiconductor integrated circuit, and more particularly, to a nonvolatile memory device having a cell on peripheral (COP) structure. Background technique [0004] Recently, memory devices with large memory capacity, smaller size, and higher integration are required. A vertical memory device or a three-dimensional memory device may include a plurality of vertically stacked memory cells to achieve a high degree of integration. In a vertical memory device, a channel may protrude or vertically extend from a surface of a substrate, and gate lines and insulating layers surrounding the vertical channel may be repeatedly st...

AI Technical Summary

Problems solved by technology

[0005] Although such a vertical structure is adopted, the size reduction of the vertical memory device is limited due to vertical contacts for connecting the memory cell array and peripheral circuits such as page buffers, row decoders, etc.

Although a vertical structure is used to increase integration, there is a limit in size reduction of the memory device due to the use of vertical contacts for connecting the memory cell array and peripheral circuits such as page buffers, row decoders, etc.

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