All-enclosed gate device and manufacturing method thereof

Abstract

The invention provides an all-enclosed gate device and a manufacturing method thereof, the method comprising the following steps: forming an insulating layer on a substrate; forming a first gate layer on the insulating layer; forming a plurality of trenches; forming a first gate dielectric layer on the upper surface of the first gate layer and the sidewall and bottom wall of the trench; form a source layer on the first gate dielectric layer; remove the part of the source layer outside the region where the trench is located; form a second gate dielectric Layered on the exposed surface of the source layer, the second and first gate dielectric layers are connected to jointly wrap the source layer; the first gate dielectric layer on the upper surface of the first gate layer is removed; the second gate layer is formed on the first On the gate layer, the second gate layer is in contact with the first gate layer to jointly wrap the gate dielectric layer and the source layer; an isolation groove is formed. The invention obtains a device structure in which the gate fully surrounds the source on the insulating buried layer, which can provide higher speed, high-efficiency operation performance and lower power consumption, has the dual advantages of FD-SOI and GAA, and reduces the cost of production.

Description

A fully enclosed gate device and method of making the same technical field [0001] The present invention belongs to the field of semiconductor device design and manufacture, and relates to a fully enclosed gate device and a manufacturing method thereof. Background technique [0002] With the increasing challenges encountered by Moore's Law, a variety of new semiconductor transistor structures have been developed, For example, three-dimensional fin field effect transistors (FINFETs), gate all around field effect transistors (Gate all around Field effect transistors) Effect Transistors, GAAFETs for short), or planar fully depleted silicon-on-insulator (FDSOI) transistors, where, The main difference between a FINFET and a planar MOSFET structure is that its channel consists of tall and thin fins raised on an insulating substrate. The source and drain electrodes are at its two ends respectively, and the tri-gate is close to its sidewall and top for auxiliary current control...

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a fully surrounded gate device and its manufacturing method, which are used to solve the problem that the computing power of the existing field effect transistor device needs to be improved, and the power consumption and production cost need to be further reduced. The problem

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