Unlock instant, AI-driven research and patent intelligence for your innovation.

ESD protection structure and preparation method thereof

An ESD protection and gate control technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve the problem of high static leakage, and achieve the effect of ultra-low leakage

Active Publication Date: 2022-04-29
MICROTERA SEMICON (GUANGZHOU) CO LTD
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a kind of ESD protection structure and preparation method thereof, be used to solve the problem that the static electric leakage of existing ESD protection structure is higher

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • ESD protection structure and preparation method thereof
  • ESD protection structure and preparation method thereof
  • ESD protection structure and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] Such as Figure 4 As shown, this embodiment provides an N-type ESD protection structure, and the N-type ESD protection structure includes: a fully depleted silicon-on-insulator 100, a silicide layer 200, a gate oxide layer 300, an isolation layer 400, a control gate 500, Programmable gate 600 , source 700 and drain 800 .

[0045] The fully depleted silicon-on-insulator 100 sequentially includes a silicon substrate 101, a buried oxide layer 102, and a top layer of silicon 103 from bottom to top, that is, the buried oxide layer 102 is formed on the upper surface of the silicon substrate 101, so The top layer of silicon 103 is formed on the upper surface of the buried oxide layer 102 ; wherein, the top layer of silicon 103 has P-type doping. In this embodiment, the thickness of the buried oxide layer 102 is 25 nm, the thickness of the top layer silicon 103 is 10 nm, and the doping concentration of P-type ions is 10 nm. -15 cm -3 .

[0046] The silicide layer 200 is fo...

Embodiment 2

[0074] This embodiment provides a P-type ESD protection structure. The difference between this structure and Embodiment 1 is that the top layer silicon 103 has N-type doping. Correspondingly, this embodiment also provides a method for preparing a P-type ESD protection structure. The difference between this method and Embodiment 1 is that the top layer silicon 103 is doped with N-type ions.

[0075] In the P-type ESD protection structure described in this embodiment, when performing ESD protection, the drain 800 is used as a cathode to receive negative ESD pulses, and the source 700, the control gate 500 and the programmable gate 600 are connected to each other Connected and connected as anode to the mains voltage (e.g. Figure 7 and Figure 8 shown). Under the action of the negative ESD pulse, the control gate 500 and the programmable gate 600 will change the barrier height of the silicide layer 200 and the top silicon 103, and at the same time, the control gate 500 will con...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides an ESD (Electro-Static Discharge) protection structure, which comprises a fully depleted silicon-on-insulator which comprises a silicon substrate, a buried oxide layer and top silicon from bottom to top; the silicide layer is formed on the upper surface of the buried oxide layer and formed on the two sides of the top layer silicon; the gate oxide layer is formed on the upper surface of the top layer silicon; the isolation layer is formed on the upper surface of part of the silicide layer and formed on the two sides of the gate oxide layer; the control gate is formed on the upper surface of a part of the gate oxide layer; the programmable gate is formed on the upper surfaces of a part of the gate oxide layer and a part of the isolation layer adjacent to the gate oxide layer, and is formed on the two sides of the control gate, and a gap is formed between the programmable gate and the control gate; the source electrode is formed on the upper surface of the silicide layer on one side of the top layer silicon and is formed on one side, far away from the programmable gate, of the isolation layer; and the drain electrode is formed on the upper surface of the silicide layer on the other side of the top layer silicon and is formed on one side, far away from the programmable gate, of the isolation layer. Through the ESD protection structure provided by the invention, the problem of high static electricity leakage of the existing structure is solved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an ESD protection structure and a preparation method thereof. Background technique [0002] The electrostatic discharge (ESD) of the chip has always been a very important link. The traditional thyristor protection and other structures can make the chip resistant to ESD. However, the static leakage of these devices is relatively high (the static leakage of the ESD device when the chip is working normally). , it is difficult to meet the requirements of ultra-low leakage, such as the leakage requirements of high-precision instrumentation amplifiers such as ultra-low bias current amplifiers. [0003] Therefore, designing an ultra-low leakage ESD protection structure has become one of the urgent technical problems to be solved by those skilled in the art. Contents of the invention [0004] In view of the above-mentioned shortcomings of the prior art, the object of the present inventio...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L27/12H01L21/84
CPCH01L27/0266H01L27/1203H01L21/84
Inventor 刘尧李建平刘筱伟班桂春刘海彬刘森
Owner MICROTERA SEMICON (GUANGZHOU) CO LTD