Semiconductor structure and forming method thereof
A technology of semiconductor and gate structure, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem that the surface of the wafer cannot provide enough area for interconnect lines and so on
Pending Publication Date: 2022-05-17
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
In order to improve integration and reduce costs, the critical dimensions of components are continuously reduced, and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines.
Method used
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Embodiment Construction
[0015] It can be seen from the background art that the devices formed so far still have the problem of poor performance. The reasons for the poor performance of the device are analyzed in conjunction with a method of forming a semiconductor structure.
[0016] refer to Figure 1 to Figure 5 , shows a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.
[0017] Such as figure 1 As shown, a base is provided, and the base includes a substrate (not shown in the figure), a fin 1 separated on the substrate, a gate structure 2 across the fin 1 , and a gate structure 2 located on the gate The source-drain doped layer 3 in the fin portion 1 on both sides of the structure 2 and the interlayer dielectric layer 4 covering the source-drain doped layer 3 , and a gate capping layer 9 is formed on the top of the gate structure 2 .
[0018] Such as figure 2 As shown, the interlayer dielectric layer 4 on the source-drain doped layer 3 ...
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Abstract
The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the gate structure is located on the substrate and parallel to the surface of the substrate, the extending direction of the gate structure is transverse, and the extending direction perpendicular to the gate structure is longitudinal; the source-drain doping layer is positioned in the substrate on two sides of the gate structure; and the source-drain lamination layer is located on the plurality of source-drain doping layers, and the source-drain lamination layer comprises a source-drain plug and a source-drain interconnection structure standing on the source-drain plug. In the embodiment of the invention, the source-drain laminated layer comprises the source-drain plug and the source-drain interconnection structure erected on the source-drain plug, that is, the source-drain plug and the source-drain interconnection structure are of an integrated structure, the adhesion between the source-drain interconnection structure and the source-drain plug is relatively strong, the corresponding strength is relatively high, and the source-drain interconnection structure and the source-drain plug are of an integrated structure, so that the manufacturing cost is reduced. Therefore, the on-resistance between the source-drain interconnection structure and the source-drain plug is small, the power consumption of the semiconductor structure is reduced, the current characteristic is improved, and the electrical performance of the semiconductor structure is optimized.
Description
technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The inte...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L27/088H01L21/768H01L23/48H01L21/8234
CPCH01L21/76805H01L21/76895H01L23/481H01L21/823475H01L21/823431H01L27/088H01L27/0886
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP