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Memory sequencer system and memory sequencing method applying same

A sequencer, memory technology, applied in the field of memory management

Pending Publication Date: 2022-05-20
SKYECHIP SDN BHD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Beyond that, the biggest challenge in scaling memory sequencer systems is addressing the ability to synchronize the different sequencers connected to the Control Center Network-On-Chip (CCNOC) so that they are programmed exactly to form wide memory interface protocols. Signal

Method used

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  • Memory sequencer system and memory sequencing method applying same
  • Memory sequencer system and memory sequencing method applying same
  • Memory sequencer system and memory sequencing method applying same

Examples

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example

[0065] Generate command, address and data sequences

[0066] Table 1:

[0067] name symbol #byte describe delay count delay 8 Number of DFI delay cycles to apply before / after the command cycle pre / post delay post_delay 1 If 1, the delay will be applied after the command cycle line command phase 0 row_sel_p0 3 Select the address sequencer corresponding to phase P0 command line phase 1 row_sel_p1 3 Select the address sequencer corresponding to phase P1 column command phase 0 col_sel_p0 3 Select the address sequencer corresponding to phase P0 Column Command Phase 1 col_sel_p1 3 Select the address sequencer corresponding to phase P1 Loop Counter Selection loop_select 2 Select 1 of 4 loop counters branch equal to zero pointer bez 3 If the selected loop counter is 0, the next table entry index branch not equal to zero pointer bnz 3 next table entry index if selected loop counter...

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Abstract

The present invention relates to a memory sequencer system (100) for an external memory protocol, the memory sequencer system (100) comprising: a control center (6) comprising a microcontroller; a control center network-on-chip (5) comprising nodes (51) connected point-to-point to synchronize and coordinate communications; the system is characterized in that: the command and address sequencer (4) is used for generating a command, a control command and an address command for a specific memory protocol; at least one data sequencer (3) for generating a pseudo-random or deterministic data pattern for each byte channel of the memory interface; wherein the command and address sequencer (4) and the data sequencer (3) are linked to form a composite address and data sequence for memory interface training, calibration and debugging; wherein the control center network-on-chip (5) interconnects the control center (6) with the command and address sequencer (4) and the data sequencer (3) to provide firmware controllability. The invention also discloses a memory sequencing method (200) for an external memory protocol.

Description

technical field [0001] The present invention generally relates to the technical field of memory management, in particular to a memory sequencer system and a memory sequence method using the system. Background technique [0002] Modern computer architectures combine three main storage technologies that dominate supercomputing: dynamic random access memory (DRAM), static random access memory (SRAM), and magnetic storage media. Magnetic storage media include hard drives and magnetic tape. Main memory is the main component used to store data within a computer and is composed almost entirely of DRAM technology. [0003] In modern computer systems, one or more DRAM memory controllers (DMCs) may be included in the processor package or integrated into a system controller that resides outside the processor package. Regardless of the location of this DRAM memory controller, its function is to accept a read or write request for a given address in memory, translate that request into o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G11C11/4076G11C19/00
CPCG06F9/30134G11C11/4076G11C19/00G06F13/1668G06F13/4027G01R31/31724
Inventor 郑誌学林舜杰
Owner SKYECHIP SDN BHD
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