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Chip power grid layout method and device, electronic equipment and readable medium

A power grid and layout method technology, applied in the computer field, can solve the problems of waste of winding resources, rework, voltage drop not meeting preset requirements, etc., and achieve the effect of reducing resource consumption and reducing the probability that the voltage drop does not meet the conditions

Active Publication Date: 2022-07-08
宏晶微电子科技股份有限公司
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if the voltage drop does not meet the preset requirements during the sign-off phase, it will often lead to waste of winding resources and rework problems

Method used

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  • Chip power grid layout method and device, electronic equipment and readable medium
  • Chip power grid layout method and device, electronic equipment and readable medium
  • Chip power grid layout method and device, electronic equipment and readable medium

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Embodiment Construction

[0023] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, but not to limit the present invention.

[0024] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] The terminology used in the present invention is used to describe specific embodiments only, and is not intended to limit the present invention. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0026] When the terms "comprising" and / or "made of" are used herein, the stated features, integers, steps, operations, elements and / or components are specified to be present, but do not preclude the presence or addition of one or more other Features, in...

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Abstract

The invention discloses a chip power grid layout method and device, electronic equipment and a readable medium. The method comprises the following steps: extracting target power grid information corresponding to a chip center of a chip, wherein the target power grid information comprises a power branch width and a power branch number; obtaining the area of the power grid based on the width of the chip center and the target power grid information; obtaining the target density of the power grid on the chip center based on the area of the chip center and the area of the power grid; determining whether the current voltage drop of the chip center meets a voltage drop condition based on the target density; and under the condition of determining that the current voltage drop meets the voltage drop condition, determining the layout of the power grid of the chip based on the target power grid information. The method can achieve the early evaluation of the voltage drop, reduces the probability that the voltage drop does not meet the condition in the acceptance stage of the chip, and reduces the resource loss.

Description

technical field [0001] The present invention relates to the field of computer technology, and in particular, to a chip power grid layout method and device, an electronic device and a computer-readable medium. Background technique [0002] Before the chip is tape-out, it must enter the sign-off stage. The sign-off stage refers to the stage in which tools are used to perform multiple checks on the chip to avoid the chip not meeting the design requirements. Among them, the voltage drop (IR drop) analysis is one of the key concerns. However, if the voltage drop does not meet the preset requirements in the sign-off stage, it often leads to waste of wiring resources and rework problems. SUMMARY OF THE INVENTION [0003] To this end, the present invention provides a chip power grid layout method and device, an electronic device and a readable medium. [0004] In order to achieve the above object, a first aspect of the present invention provides a chip power grid layout method....

Claims

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Application Information

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IPC IPC(8): G06F30/392H01L27/02G01R31/28G01R19/00G06F115/02
CPCG06F30/392H01L27/0207G01R31/2851G01R19/0084G06F2115/02Y02E60/00
Inventor 张凤林刘伟
Owner 宏晶微电子科技股份有限公司
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