Continuous time linear equalization adaptation algorithm supporting baud rate clock data recovery locked to eye center

Abstract

Apparatus and related methods involve employing a continuous time linear equalization circuit with a minimum mean square error baud rate clock and a data recovery circuit to enable locking to or near the center of the eye pattern. In an illustrative example, a circuit may include: an inter-symbol interference (ISI) detector configured to receive data and error samples; a summing circuit coupled to an output of the ISI detector; a moving average filter configured to receive an output of the summing circuit and generate an average output; a voter configured to generate a vote in response to the average output and a predetermined threshold; and an accumulator and a code generator configured to generate a code signal in response to the generated votes. By introducing a moving average filter and a voter, a faster method of locking to or approaching the center of the eye pattern can be obtained.

Description

technical field [0001] Various embodiments relate generally to electronic circuits, and in particular to clock data recovery (CDR) circuits in receivers. Background technique [0002] Clock data recovery (CDR) circuits are important modules in receiver systems for high-speed serial communications. The CDR circuit can generate the correct sampling clock phase for data recovery. The quality of high-speed serial communication links can be sensitive to the sampling dock phase, especially in the presence of jitter and noise. [0003] In a receiver with a phase interpolator that determines the phase of the clock used to sample the input data, the CDR circuit can be used to identify whether the currently used docking phase is the best docking phase to capture the input data. The CDR circuit can provide dynamic phase adjustment for the phase interpolator. The CDR circuit can operate to move the docking phase position towards the center of the data eye. The further the current do...

AI Technical Summary

Problems solved by technology

The resulting oversampled system may consume more clock power than a system running at symbol rate (also known as baud rate)

Also, as the channel loss distribution varies, the analog waveform to be sampled may not necessarily be symmetrical

Therefore, it may not be optimal to keep the data sampling docking centered between the zero crossings

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