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Low-on-resistance SGT preparation method, semiconductor device and equipment

A low on-resistance, conductive plug technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc. Difficult to eliminate, main on-resistance reduction effect

Pending Publication Date: 2022-08-05
上海芯导电子科技股份有限公司
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AI Technical Summary

Problems solved by technology

[0005] The invention provides a method for preparing SGT with low on-resistance, semiconductor device and equipment, so as to solve the problem that substrate resistance is difficult to eliminate

Method used

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  • Low-on-resistance SGT preparation method, semiconductor device and equipment
  • Low-on-resistance SGT preparation method, semiconductor device and equipment
  • Low-on-resistance SGT preparation method, semiconductor device and equipment

Examples

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preparation example Construction

[0064] The preparation technology of prior art SGT product is:

[0065] growing an epitaxial layer on a substrate;

[0066] A hard mask layer and a photoresist are sequentially deposited on the substrate, the photoresist is patterned, and the hard mask layer is etched using the patterned photoresist as a mask to form a patterned hard mask layer for patterning The hard mask layer is a mask to etch the epitaxial layer, remove the photoresist, and form a gate trench;

[0067] growing an oxide layer on the surface of the substrate and in the gate trench, and then forming a shielding gate, an oxide layer between gates and a gate in the gate trench in sequence;

[0068] Implanting P-type ions and N-type ions in the epitaxial layer around the gate to form source and well regions;

[0069] Deposit an interlayer dielectric layer on the surface of the epitaxial layer and the top of the gate, coat photoresist on the surface of the interlayer dielectric layer, pattern the photoresist, a...

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Abstract

The invention provides a preparation method of an SGT with low on-resistance. The preparation method comprises the following steps: sequentially forming a stacking layer of an interlayer dielectric layer, a first epitaxial layer and a second epitaxial layer on a substrate; a well region and a source region are formed in the first epitaxial layer; a plurality of gate trenches are formed, a first oxide layer is grown, and the first oxide layer covers the side walls of all the gate trenches and the top of the second epitaxial layer; forming a grid electrode in the grid electrode groove; all the grid electrodes in a part of the grid electrode groove are etched, an inter-grid oxide layer grows, and the inter-grid oxide layer covers the top of the grid electrode; forming a shield gate in the gate trench; forming a patterned second oxide layer to cover the top of the shield gate; forming a third epitaxial layer which covers the second epitaxial layer; the substrate is thinned; a plurality of conductive plugs are formed in the substrate. Therefore, according to the preparation method provided by the invention, the substrate resistance is eliminated, the problem that the substrate resistance is difficult to eliminate is solved, and the main on-resistance of the device is reduced.

Description

technical field [0001] The present invention relates to the field of semiconductor devices, in particular to a method for preparing SGT with low on-resistance, a semiconductor device and equipment. Background technique [0002] At present, the on-resistance of SGT (split gate trench MOSFET, shielded gate trench-metal oxide field effect transistor) products is composed of: Rdson=Rcontact+Rsource+Rch+RA+Rmesa+Rd+Rsub, where Rdson is on Resistance, Rcontact is the contact resistance, Rsource is the source resistance, Rch is the channel resistance, RA is the accumulation region resistance, Rmesa is the drift region resistance between trenches, Rd is the drift region resistance, Rsub is the substrate resistance; in SGT products The main components of the on-resistance Rdson are Rch, Rd and Rsub. [0003] In the existing SGT preparation process, there are certain limitations in thinning the substrate. If the thinning is excessive, the wafer of the substrate is prone to debris. Th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/77H01L23/48H01L27/12
CPCH01L23/481H01L27/124H01L27/1262H01L27/1218
Inventor 陈敏戴维欧新华袁琼庞艳楠夏杰吴佳吴晨雨
Owner 上海芯导电子科技股份有限公司
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