Wiring structure and method for wafer substrate standard integration area suitable for on-chip integration

Abstract

The invention discloses a wafer substrate standard integration area wiring structure and method suitable for on-chip integration, the wafer substrate standard integration area wiring structure comprises a core voltage network, an interconnection signal network, a clock signal network and a ground wire network, the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a middle metal layer, and the ground wire network is located in the middle metal layer. The ground wire network is located on the bottom metal layer. Pins provided upwards by the standard integration area comprise a core voltage pin, an interconnection signal pin, a clock signal pin, a ground wire pin and a complex function pin, the complex function pin is directly connected to the outside of the system through a TSV at the bottom of a wafer, and the other pins are connected through a signal network to which the pins belong; the core voltage pins and the ground wire pins are distributed in a centrosymmetric #-shaped core voltage area in a stripe staggering mode, and the interconnection signal pins are distributed in an interconnection signal area around a standard integration area. According to the invention, the problem of low yield of metal wiring of the wafer substrate caused by a large number of wiring layers and lack of wiring planning is solved.

Description

technical field [0001] The present invention relates to the technical fields of micro-nano processing, redistribution layer (RDL) and on-chip integration, in particular to a wafer substrate standard integrated area wiring structure and method suitable for on-chip integration. Background technique [0002] With the gradual failure of Moore's Law and Dennard's Law of Scaling, the improvement of computing performance by technological progress has slowed down significantly, while the amount of data in the Internet of Everything has exploded exponentially, and the "scissors" gap between data scale and computing power is getting wider and wider. The larger the integrated circuit, the period of major technological and industrial changes in the "post-Moore era" is coming. [0003] In view of the unsustainable problem of Moore's Law, the System on Wafer (SOW) has attracted the attention of academia and industry, and used it to expand Moore's Law. Its main connotation is to directly ...

AI Technical Summary

Problems solved by technology

Secondly, despite controlling the size of the photomask, under the condition of too many metal layers, a high yield cannot be guaranteed

Studies have shown that even if the number of metal layers is controlled to 4 layers, the yield rate is only 85.11% at a metal utilization rate of 10%

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