Dual hard mask CMP technology for eliminating influence of silicon cone phenomenon
A hard mask and process technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of polysilicon wiring process influence, low grinding speed, and inability to planarize silicon cones, etc., to achieve favorable control and effect, the effect of improving the yield
Inactive Publication Date: 2004-12-29
SHANGHAI HUA HONG GROUP +1
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Problems solved by technology
[0004] STI silicon oxide over-grinding (Disching) problem: Due to the influence of pattern density, the grinding rate of CMP process is different in different pattern areas. In the area with higher pattern density in the active area, the grinding speed lower
After filling the isolation dielectric, the shape of the silicon cone will be preserved on the surface of the trench dielectric, and due to the existence of the field protection hard mask in the wide trench area, the silicon cone cannot be effectively planarized during the CMP process. The remaining silicon cone will affect the subsequent polysilicon wiring process
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[0025] Implementation steps of the present invention are as follows:
[0026] 1. Deposit the buffer layer silicon oxide by dry oxidation method; deposit silicon nitride by low pressure CVD method;
[0027] 2. Photolithography step, the first step is hard mask etching and silicon groove etching.
[0028] 3. High-density plasma chemical vapor deposition method to fill the isolation groove dielectric.
[0029] 4. Secondary silicon nitride deposition.
[0030] 5. Field protection hard mask photolithography and etching, using a mask plate with a mesh structure; producing a field protection hard mask with a mesh structure in the isolation groove area.
[0031] 6. Silicon oxide CMP process.
[0032] 7. Wet etching the hard mask.
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Description
technical field [0001] The invention belongs to the technical field of integrated circuit technology, and in particular relates to a double hard mask CMP technology capable of eliminating the influence of the silicon cone phenomenon. Background technique [0002] In the process of semiconductor integrated circuits, the traditional isolation technology is self-aligned field oxidation isolation technology, that is, the active area is covered with a hard mask, the substrate silicon in the field area is exposed, and then the isolation area is oxidized by thermal oxidation. silicon. This method is simple, highly productive, and the production process used is mature. The disadvantage is that a 'bird's beak' area will be formed at the boundary of the active area, such as figure 1 Shown becomes a bottleneck in the development of deep submicron technology to increase the degree of integration. [0003] In practice, it is difficult to reduce the size of the 'beak' to below 0.1 μm. ...
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IPC IPC(8): H01L21/304H01L21/76
Inventor 金虎张征
Owner SHANGHAI HUA HONG GROUP