Method for forming grid structure and self-aligning contact hole structure and forming method thereof

Abstract

A method for forming a gate structure and a self-aligned contact hole structure, comprising the following steps: depositing a first conductive layer on a substrate; depositing a second conductive layer on the first conductive layer; depositing a second conductive layer on the second depositing an insulating layer on the conductive layer; performing photolithography and etching processes to remove selected portions of the insulating layer; etching a portion of the second conductive layer without etching to its lower surface; etching a portion of the remaining second conductive layer and The first conductive layer is used to form a plurality of gate structures; a sidewall spacer layer is formed on the sidewalls of each gate structure; a dielectric layer covering all gate structures is formed; and the gate structures are removed between the gate structures and forming a self-aligned hole between selected portions of the dielectric layer until the surface of the substrate is exposed; and forming a metal layer covering the hole, and the exposed liner between the metal layer and the substrate The bottom surface makes contact.

Description

technical field [0001] The present invention relates to a kind of method of forming gate structure and self-aligned contact hole structure; Specifically, the present invention relates to a method for removing the gate conductor / bit line contact hole (gate conductor / Shortcomings of bitline contact, GC / CB) and a method of increasing a larger process window. Background technique [0002] Generally, a metal oxide semiconductor (MOS) device is composed of a metal layer, a silicon oxide layer and a substrate. Due to poor adhesion between metal and oxide, polysilicon is often used instead of metal to form the conductive layer of the gate structure of the MOS device. However, the disadvantage of polysilicon is that its resistance is higher than that of metals. Although it can be doped with impurities to reduce the resistance, the resulting conductivity still cannot be used as a good conductive layer in MOS devices. A common solution is to add a layer of metal silicide, such as tu...

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Problems solved by technology

However, if the etching time is not properly controlled, this method will cause the insulating layer 8 and the sidewall spacer 10 to be over-etched, and the second conductive material layer 6 below it will be exposed.

The exposed portion of the second conductive material layer 6 will contact the metal layer 14 at point 16 to cause a short circuit

[0015] However, the method for forming the self-aligned contact hole structure provided by U.S. Patent No. 5,989,987 has the following disadvantages: (1) the etching step for the second conductive material layer 6 will also etch the first conductive material layer 4 at a slower rate , so that its critical dimension (critical dimension) is reduced, the channel length (channel length) is reduced, and the critical voltage (VT) is reduced; (2) Since the cross-sectional area of ​​the second conductive material layer 6 becomes smaller, the gate conductor (3) This etching step will cause the contact area between the second conductive material layer 6 and the first conductive material layer 4 to decrease, if the contact area decreases too much, it will cause peeling (peeling) phenomenon

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