High density semiconductor memory having diagonal bit lines and dual word lines

Abstract

Disclosed is a high density semiconductor memory having diagonal bit lines and a dual word line configuration. The present invention relates to The semiconductor memory includes a memory cell array of memory cells arranged in rows and columns, and a plurality of diagonal bit lines arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines, where each dual word line includes a master word line at a first layer and a plurality of local word lines at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections, and each local word line is connected to plural memory cells. The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.

Description

technical field [0001] The present invention generally relates to semiconductor memories such as dynamic random access memories (DRAMs). In particular, it relates to a space efficient structure for high density semiconductor memory having diagonal bit lines to facilitate access to memory cells, and double word lines on different vertically separated layers. Background technique [0002] Because there is a constant tendency to increase the capacity of semiconductor memories, new designs are required that save space on chips without compromising their performance. As smaller and smaller memory cells are realized, the problem of efficiently accessing the cells using wordlines and bitlines without additionally impacting the size of the chip becomes more and more challenging. [0003] Traditional DRAM chips use millions of memory cells arranged in rows and columns in one or more arrays, with bit lines parallel to the columns and word lines parallel to the rows. Each memory cell...

AI Technical Summary

Problems solved by technology

[0011] exist Figure 1A In the structure of , the staggered pattern of bit lines connected to the local word line driver units between multiple memory blocks results in wasted chip area at the region Ap at the edge of each memory block

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