Structure and manufacture of ROM with tunneling dielectric layer of high dielectric constant

Abstract

The present invention is the structure and manufacture of ROM with tunneling dielectric layer of high dielectric constant. The manufacture includes forming tunneling dielectric layer of HfOxNy or HfSiON on a substrate; subsequent forming charge trapping layer and top oxide layer successively on the tunneling dielectric layer; defining top oxide layer, floating grid layer and tunneling dielectric layer to form several stack structures; forming doped are in the substrate in the stack structures; forming embedded drain oxide layer on the surface of doped area; and forming conductor pattern layer as the character lines of ROM on the substrate.

Description

technical field [0001] The present invention relates to a structure and a manufacturing method of an integrated circuit (Integrated circuit, IC), and in particular to a structure of a read-only memory with a high-k tunneling dielectric layer (High-Ktunneling dielectric) and manufacturing method. Background technique [0002] The development trend of today's semiconductor industry is towards the direction of reducing the size of semiconductor components, because the reduction of component size can increase the integration of semiconductor components, enhance the function of integrated circuits, reduce the cost of its use, improve the switching speed of components and reduce components. Power consumption and other advantages. As the size of semiconductor devices shrinks, in order to maintain the capacitance between the gate and the channel, the thickness of the dielectric layer (oxide layer) between the gate and the substrate must also be adjusted to be thinner. [0003] For...

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Problems solved by technology

As mentioned above, as the size of the read-only memory element shrinks, the thickness of the tunnel oxide layer must be correspondingly thinned. However, the thickness of the tunnel oxide layer has a lower limit, that is, it must have a certain thickness , when the thickness of the tunnel oxide layer is less than the lower limit, it will cause many problems

For example, in the subsequent thermal process, the too thin tunnel oxide layer will not be able to prevent oxygen or dopants from diffusing into the substrate or trapped in the tunnel oxide layer, thereby changing the initial voltage of the device. In addition, when the thickness of the tunnel oxide layer is less than the lower limit, due to poor retention properties of the tunnel oxide layer, electrons stored in the charge trapping layer may also pass through the tunnel Flow through the oxide layer to the substrate, resulting in the loss of stored data and leakage current

Therefore, it can be known from the above that the read-only memory device will be limited by the minimum thickness of the tunnel oxide layer (silicon dioxide) and cannot continue to shrink down.

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