Grinding process for back of wafer

A back-grinding and wafer technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of wafer 20 fragmentation, collision damage, displacement deviation, etc., to reduce handling actions and prevent warpage and breakage. The effect of cracking and preventing chipping

Inactive Publication Date: 2007-02-07
CHIPMOS TECH INC +1
View PDF3 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the known small size, such as 4in or 6in wafers, the wafer warpage (wafer war page) after back grinding is still not obvious, especially in the acceptable range, but as the wafer size increases, such as 6in Above, or the thickness of the grinding is more stringent, such as below 12 mils, such as figure 2 As shown, the warping of the wafer 20 after grinding is quite obvious, and the occurrence of this warping is more serious due to the residual stress of the wafer integrated circuit process and the thinning of the semiconductor base layer such as silicon, so that after the wafer is removed The wafer 20 is easily broken in the fourth step of the circle or in the subsequent handling steps.
[0026] The discl

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Grinding process for back of wafer
  • Grinding process for back of wafer
  • Grinding process for back of wafer

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0052] Such as image 3 , Picture 11 , Picture 12 As shown, the present invention includes the following steps:

[0053] step one

[0054] Provide wafer

[0055] Such as Figure 4 As shown, a wafer 50 with an active surface 51 and a corresponding back surface 52 is prepared. On the active surface 51, integrated circuits have been fabricated, such as microprocessors, microcontrollers, memory, or integrated circuits for special applications. Preferably, the wafer 50 is a high frequency memory, such as a random access memory such as DDR, Rambus, TDR, or QDR. The size of the wafer can be 4in, 5in, 6in, 8in or 12in. Preferably, the wafer is 8in or 12in; preferably a removable adhesive protective tape 53 is attached to the active surface 51 of the wafer 50 .

[0056] Step two

[0057] Load wafer

[0058] Such as Figure 5 As shown, the wafer 50 is loaded on the grinding chuck 61 of the wafer back grinding equipment 90 by vacuum adsorption or electrostatic adsorption or other adsorption...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The wafer back side grinding process is one integrated semiconductor manufacture process capable of avoiding warping and damage of wafer and accurate positioning. The process includes the following steps: providing wafer with active side and back side, loading the wafer via adsorption onto the grinding plate to expose the back side of wafer, grinding the back side of wafer, adhering positioning part to the ground wafer back side, and unloading the wafer via eliminating the adsorption force of the grinding plate. During the step of adhering positioning part to the ground wafer back side, the adsorption force is maintained, and in the step of unloading the wafer the positioning part is used as carrier for shifting the wafer.

Description

technical field [0001] The invention belongs to semiconductor technology, in particular to a wafer back grinding technology. Background technique [0002] With the thinning trend of semiconductor package components, the chips in the package components also need to comply with thinner thickness. Therefore, a wafer backside grinding process is proposed. The conventional wafer back grinding process is implemented after the integrated circuit manufacturing process and before the wafer dicing process, so that multiple chips on the wafer can be thinned at one time. [0003] like figure 1 , figure 2 As shown, the traditional wafer back grinding process and wafer cutting process include the following steps: [0004] step one [0005] Provide wafer [0006] A wafer 20 having an active surface 21 for forming an integrated circuit and a corresponding back surface 22 is provided, and a protective tape 23 is usually pasted on the active surface 21 of the wafer 20 . [0007] step ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/304B24B1/00
Inventor 顾沛川鲁明联李崇豪
Owner CHIPMOS TECH INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products