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High dielectric grid laminating structure

A high-dielectric layer, high-dielectric technology, applied in the manufacture of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems such as the tunnel current cannot be completely suppressed, the carrier mobility is reduced, and the thickness is reduced. Achieve the effect of reducing gate tunneling current, simple IC manufacturing process, and low power consumption

Inactive Publication Date: 2007-05-30
SHANGHAI HUA HONG GROUP +1
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  • Description
  • Claims
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Problems solved by technology

[0011] The purpose of the present invention is to design a sandwich gate dielectric structure for low power consumption devices, so as to solve the shortcomings that cannot be overcome by a single high dielectric material: interface problems or low K values---resulting in carrier mobility Reduced and equivalent SiO 2 Thickness (t eq ) decreases, the tunneling current cannot be completely suppressed

Method used

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  • High dielectric grid laminating structure

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Embodiment Construction

[0022] The present invention is further described below by specific embodiment:

[0023] l. Chip surface cleaning: first remove the natural SiO on the surface of the silicon wafer 2 Remove with HF steam;

[0024] 2. Al 2 O 3 Interfacial Defining Layer Growth: Using Atomic Layer Growth (ALCVD) or Metal Organic Vapor Deposition (MOCVD) to grow about 0.5nm Al on the surface hydrogenated silicon wafer 2 O 3 as the interface defining layer;

[0025] 3. Ta 2 O 5 or SrTiO 3 Deposition: use ALCVD or MOCVD or sol-gel (Sol-gel) method to deposit Ta about 3nm 2 O 5 Or about 75nm SrTiO 3 ; The thickness can be adjusted according to the equivalent gate oxide thickness;

[0026] 4. Al 2 O 3 Overlay growth: use ALCVD or MOCVD to deposit Al about 0.5nm 2 O 3 as an overlay;

[0027] 5. Metal gate deposition: use low temperature process (<600°C) CVD method to deposit metal gate, such as Ta or TaN or TiN.

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Abstract

A laminated high-dielectric grid structure is disclosed for decreasing the current leakage of grid oxide layer. It features its sandwich structure, that is, Al2O3 / M / Al2O3 structure, where M is Ta2O5 or SrTiO3 which has high dielectric constant. In addition, the Ta or TaN or TiN is used as electrode for preventing the depletion of polysilicon and B breakthrough.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and particularly relates to a high-k stack structure of a high-dielectric gate. Background technique [0002] In the CMOS IC manufacturing process, the continuous shrinking of the unit device requires the continuous reduction of the thickness of the gate dielectric. This requirement comes from two considerations: 1. Controlling short-channel effects; 2. Implementing high-current drive—while maintaining a sufficiently large amount of induced charge in the channel while the supply voltage is reduced. In both cases, the electrical thickness of the gate dielectric is important in terms of first-order approximation. The electrical thickness during inversion is determined by three series capacitances, namely: the depletion capacitance of the gate electrode, the capacitance of the gate dielectric and the capacitance of the inversion layer of the silicon...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/285
Inventor 缪炳有徐小诚
Owner SHANGHAI HUA HONG GROUP