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High dielectric grid laminating structure

A high-dielectric layer and high-dielectric technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve the problem that the tunneling current cannot be completely suppressed, the carrier mobility is reduced, and the K value is low, etc. problem, to achieve the effect of reducing gate tunneling current, simple IC manufacturing process, and easy integration

Inactive Publication Date: 2003-06-18
SHANGHAI HUA HONG GROUP +1
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Problems solved by technology

[0010] The purpose of the present invention is to design a sandwich gate dielectric structure for low power consumption devices, so as to solve the shortcomings that cannot be overcome by a single high dielectric material: interface problems or low K values---resulting in carrier mobility Reduced and equivalent SiO 2 Thickness (t eq ) decreases, the tunneling current cannot be completely suppressed

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  • High dielectric grid laminating structure
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specific Embodiment approach

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is further described below through specific examples:

[0022] 1. Chip surface cleaning: first clean the natural SiO on the surface of the silicon wafer 2 Remove with HF steam;

[0023] 2. Al 2 o 3 Interface-determined layer growth: grow about 0.5nm Al on the surface hydrogenated silicon wafer by atomic layer growth method (ALCVD) or metal organic vapor deposition method (MOCVD) 2 o 3 As an interface determination layer;

[0024] 3. Ta 2 o 5 or SrTiO 3 Deposition: use ALCVD or MOCVD or sol-gel (Sol-gel) method to deposit about 3nm Ta 2 o 5 Or SrTiO around 75nm 3 ; The thickness can be adjusted according to the equivalent gate oxide thickness;

[0025] 4. Al 2 o 3 Covering layer growth: Deposit about 0.5nm Al by ALCVD or MOCVD method 2 o 3 as an overlay;

[0026] 5. Metal gate deposition: use low temperature process (<600°C) CVD method to deposit metal gate, such as Ta or TaN or TiN.

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Abstract

A laminated high-dielectric grid structure is disclosed for decreasing the current leakage of grid oxide layer. It features its sandwich structure, that is, Al2O3 / M / Al2O3 structure, where M is Ta2O5 or SrTiO3 which has high dielectric constant. In addition, the Ta or TaN or TiN is used as electrode for preventing the depletion of polysilicon and B breakthrough.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a high-k stack structure of a high dielectric gate. Background technique [0002] In the CMOS IC manufacturing process, the continuous reduction of unit devices requires the continuous reduction of gate dielectric thickness. This requirement comes from two considerations: 1. Controlling the short channel effect; 2. Realizing high current drive --- while the supply voltage is reduced, the amount of induced charges in the channel is still kept sufficiently large. In both cases, to a first approximation, the electrical thickness of the gate dielectric is important. The electrical thickness during inversion is determined by three series capacitances, namely: the depletion capacitance of the gate electrode, the capacitance of the gate dielectric and the capacitance of the inversion layer of the silicon substrate, such as ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/285
Inventor 缪炳有徐小诚
Owner SHANGHAI HUA HONG GROUP