Structure of grid medium with high dielectric and its preparation method
A high-dielectric and gate-dielectric technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve the problem that the tunneling current cannot be completely suppressed, the interface problem or the K value is low, and the carrier mobility is reduced etc. to achieve the effects of reducing gate tunneling current, low power consumption, and simple manufacturing process
Inactive Publication Date: 2003-05-07
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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[0010] The purpose of the present invention is to propose a high-dielectric gate dielectric structure and its preparation method for low-power devices, so as to solve the shortcomings that cannot be overcome by a single high-dielectric material: interface problems or low K values--- resulting in reduced carrier mobility and equivalent SiO 2 Thickness (t eq ) decreases, the tunneling current cannot be completely suppressed
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[0020] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is further specifically described below by way of examples:
[0021] 1. Surface cleaning of silicon wafers: first clean the natural SiO on the surface of silicon wafers 2 Remove with HF steam;
[0022] 2. Al 2 o 3 Interface-determined layer growth: grow about 0.5nm Al on the surface hydrogenated silicon wafer by atomic layer growth method (ALCVD) or metal organic vapor deposition method (MOCVD) 2 o 3 As an interface defining layer; for example, with Al(CH 3 ) 3 and water vapor deposition;
[0023] 3.BaO+Al 2 o 3 Deposition: Deposit BaO+Al with a thickness of about 4nm by ALCVD or MOCVD or sol-gel (Sol-gel) method 2 o 3 ; The thickness can be adjusted according to the equivalent gate oxide thickness; for example, use Ba(CH 3 ) 2 , Al(CH 3 ) 3 and oxygen or ozone deposition;
[0024] 4. Metal gate deposition: TiN metal gate is deposited by low temperature process (<600°C) CVD method.
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Abstract
Along with continuous reducing in the size of the parts, when the thickenss of the silicon dioxide of the grid less than 1.5 nm, the leakage current passing through the grid is too large so as to have to seek for the high dielectric material to replace the silicon dioxide. But, it is difficult to meet the requirement by using the single layer of the material. Thus, the combination of the multiple layers of dielectric materials is the feasible scheme. The two-layer structure of the grid dielectric material is designed in the invention that is the structure Al2O3 / BaO+Al2O3. The band gap of Al2O3 is 8.8eV with the dielectric constant 0-10 the offset of the conduction band 2.8eV. The parameters of Al2O3 similar to SiO2 are suitable for being as the boundary layer.
Description
technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a high-k stack structure of a high dielectric gate. Background technique [0002] In the CMOS IC manufacturing process, the continuous shrinkage of unit devices requires the continuous reduction of gate dielectric thickness. This requirement comes from two considerations: 1. Controlling the short channel effect; 2. Realizing high current drive --- while the supply voltage is reduced, the amount of induced charges in the channel is still kept sufficiently large. In both cases, to a first approximation, the electrical thickness of the gate dielectric is important. The electrical thickness during inversion is determined by three series capacitances, namely: the depletion capacitance of the gate electrode, the capacitance of the gate dielectric and the capacitance of the inversion layer of the silicon substrate, such as ...
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IPC IPC(8): H01L21/283H01L21/82
Inventor 缪炳有徐小诚
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT