Multistage amplifier
A multi-stage amplifier and final-stage amplifier technology, applied in the direction of amplifiers, improving amplifiers to improve efficiency, improving amplifiers to reduce nonlinear distortion, etc., can solve the problem of reducing the gain of distortion compensation circuit 2, and cannot obtain large distortion compensation effects problem, to achieve the effect of large distortion compensation and improve efficiency
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0034] image 3 is a configuration diagram showing a multi-stage amplifier according to Embodiment 1 of the present invention. In the figure, 11 is an input terminal, 12 is a first-stage amplifier composed of a gate bias circuit, a drain bias circuit, a matching circuit, etc., in addition to an amplifying element such as a GaAsFET or a HEMT (high electron mobility transistor), and 13 Is the terminal between the first stage amplifier 12 and the second stage amplifier 14, 14 is the same second stage amplifier as the first stage amplifier 12, 15 is the terminal between the second stage amplifier 14 and the final stage amplifier 16, 16 It is the same final stage amplifier as the first stage amplifier 12 .
[0035] Wherein, as the bias condition of the first-stage amplifier 12, the no-load current Ido is set to be less than one-tenth of the saturation current Idss.
[0036] Second, explain its working.
[0037] Figure 4 It is an explanatory diagram showing the dependence of th...
Embodiment 2
[0062] In Embodiment 1 above, there is no mention of the gate width Wg1 of the transistor of the first-stage amplifier 12 , but Wg1 can be set as follows using the relationship with the gate width Wg3 of the transistor of the final-stage amplifier 16 .
[0063] Wg1>2.4×Wg3 / (Gain2×Gain3)
[0064] The details are as follows.
[0065] The working level of the first-stage amplifier 12 whose bias condition is set as Ido<0.1Idss is the same as the usual situation, and compared with the working level of the final-stage amplifier 16 in the same way as the usual situation, it is set to increase by 3dB left and right compensation levels.
[0066] However, when the bias condition is set to Ido0.75Idss, it is necessary to use a large gate of about 1dB compared with the case of normal bias conditions. extremely wide transistors.
[0067] When the gate width of the transistor of the final-stage amplifier 16 is denoted as Wg3, since the gain of the second-stage amplifier 14 and subsequent...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 