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Semiconductor element structure

A technology of semiconductors and components, which is applied in the field of metal-oxide-semiconductor transistor component structures, can solve problems such as component performance degradation, and achieve the effects of performance improvement, channel width increase, and channel current increase

Inactive Publication Date: 2003-08-13
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, if the channel width becomes smaller as the device shrinks, the channel current between the source / drain 12 and 13 will decrease during operation, thereby deteriorating the device performance

Method used

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  • Semiconductor element structure
  • Semiconductor element structure
  • Semiconductor element structure

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Experimental program
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Embodiment Construction

[0031] figure 2 It is a top view of the metal oxide semiconductor transistor structure 30 of the embodiment of the present invention. The MOS transistor 30 includes a hollow closed gate 60 located on a semiconductor substrate (not shown). The hollow closed grid 60 includes a head 60a and a tail 60b, so that the hollow closed grid 60 is similar to a P-shape from a top view. Wherein the head 60a is a square with a hollow closed space, but the structure of the head 60a is not limited to a square, it can also be a hollow structure (not shown in the figure) of a rectangle, a circle, a hexagon, an octagon or other shapes. . The hollow closed gate 60 is fabricated by known techniques, such as thermally growing a pad oxide layer on the active region 31 of a P-type substrate, and its thickness is about 50 angstroms to 300 angstroms. Then perform a channel threshold adjustment ion implantation (Channel Threshold Adjust Implantation), implanted ion species, such as boron ions or boro...

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Abstract

A semiconductor element structure is a MOS one with enclosed hollow gate structure on a semiconductor substrate to form a cavity. The dielectric layer of gate is positioned between said gate and substrate. The drain region is in said cavity in the semiconductor substrate. The source region surrounds said gate in the semiconductor substrate.

Description

technical field [0001] The present invention relates to a semiconductor device, and in particular to a Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) device structure with lower junction capacitance (Junction Capacitance). Background technique [0002] During the operation of the metal-oxide-semiconductor transistor device, parasitic junction capacitance (Parasitic Junction Capacitance) of the source / drain region is generated on both sides of the depletion region (Depletion Region) between the source / drain region and the substrate. The junction capacitance is roughly proportional to the area of ​​the source / drain region. During the logic transition (Logic Transition) of the transistor, the junction capacitance will have a bad influence on the switching speed of the transistor (Switching Speed). This is because each time the transistor switches between logic states, the junction capacitance will charge and Discharge, thus seriously reducing the performance of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78
Inventor 谢宗轩张耀文卢道政
Owner MACRONIX INT CO LTD