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Method for detecting semiconductor device and semiconductor storage device

A semiconductor and device technology, applied in the field of semiconductor devices for CBCM circuits, can solve the problems of reduced measurement accuracy of target capacitance Ct, large gate-stop leakage, and inability to increase leakage current, etc.

Inactive Publication Date: 2003-08-27
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, even if the thickness of the gate insulating film is reduced, the leakage current at the time of ON cannot be increased.
In the CBCM method, if a transistor with a gate insulating film thickness of about 2nm is used, the gate-off leakage will be large, so the same phenomenon occurs as Figure 35 The same phenomenon, but there is a problem that the measurement accuracy of the target capacitance Ct is lowered

Method used

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  • Method for detecting semiconductor device and semiconductor storage device
  • Method for detecting semiconductor device and semiconductor storage device
  • Method for detecting semiconductor device and semiconductor storage device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0087] The semiconductor device for CBCM according to Embodiment 1 of the present invention is characterized in that the gate-off leakage current is smaller than that of other logic transistors mounted on the same chip. Furthermore, it is characterized by a structure in which noise caused by the interface of the semiconductor substrate and the gate insulating film is reduced.

[0088] As will be described in detail below, the semiconductor device for CBCM according to Embodiment 1 of the present invention has the effect of improving the measurement accuracy of the target capacitance because the gate-off leakage current and noise are reduced compared with the conventional structure.

[0089] (existing structure)

[0090] figure 1 It is a cross-sectional view showing a cross-sectional structure of a conventional MOS transistor for a semiconductor device for CBCM. As shown, well region 2 is formed on silicon substrate 1 , channel barrier layer 3 is formed on well region 2 , an...

Embodiment 2

[0146] Embodiment 2 of the present invention is characterized in that the source voltage switching unit is connected to the source of the CBCM transistor. There is an advantage that the holding current during standby can be reduced by adjusting the source potential by the source switching unit.

[0147] (first mode)

[0148] Figure 12 It is a cross-sectional view of a first mode structure of a semiconductor device for CBCM as a second embodiment of the present invention.

[0149] As shown in the figure, in the semiconductor device shown in the first mode, source voltage switching sections 31 to 34 as power supply connection switching sections are arranged on the sources of the respective NMOS transistors of CBCMTEG (Test Element Group) 25 .

[0150] The source voltage switching section 31 switches and controls the source voltage of the PMOS transistor MP1, the source voltage switching section 32 switches and controls the source voltage of the NMOS transistor MN1, and the so...

Embodiment 3

[0190] The semiconductor device according to the third embodiment of the present invention is characterized in that the CBCM circuit and the pad for measuring the LCR meter are connected by the same wiring.

[0191] According to the semiconductor device of the third embodiment, since the capacitance of the same wiring can be measured by both the CBCM and the LCR meter, it is possible to eliminate variations due to processing and obtain a correlation between the two.

[0192] Conventionally, two wiring patterns were prepared, and the circuits for CBCM and the pads for LCR meters were connected independently to each other so that the layout had the same capacitance. Even if the wiring capacitance is the same in the layout, since the wiring structure of the finish processing after the wafer processing is finished varies due to processing, some wiring capacitances are often different. Therefore, even if the wiring structure with the same wiring capacitance in the layout is measure...

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Abstract

It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4') are selectively formed in a surface of a body region (16), and extension regions (5) and (5') are extended from tip portions of the source-drain regions (4) and (4') opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4') including the extension regions (5) and (5') and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6') in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5') and a peripheral portion of the extension region (5).

Description

technical field [0001] The present invention generally relates to a semiconductor device having a function of measuring various capacitances such as wiring capacitance, gate capacitance, and junction capacitance, and more particularly to a semiconductor device having a circuit for CBCM using a CBCM (charge-based capacitance measurement) method as a capacitance measurement method device. Background technique [0002] (Principle of CBCM method) [0003] Figure 33 This is a circuit diagram showing a circuit configuration for CBCM in a semiconductor device using the conventional CBCM method. As shown in the figure, the PMOS transistor MP1 and the NMOS transistor MN1 are connected in series, and the PMOS transistor MP2 and the NMOS transistor MN2 are connected in series. Furthermore, the source of the PMOS transistor MP1 is connected to the pad 52 , the source of the PMOS transistor MP2 is connected to the pad 54 , and the sources of the NMOS transistors MN1 and MN2 are common...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/76H01L21/822H01L21/8238H01L27/04H01L27/08H01L27/092H01L27/10H01L29/10H01L29/78H10B12/00
CPCH01L21/823807H01L2924/0002H01L27/092H01L21/823814H01L29/7801H01L29/1045H01L29/66507H01L29/7833H01L29/1083H01L29/6659H01L29/6656H01L29/105H01L2924/00H01L21/18
Inventor 国清辰也永久克己山下恭司海本博之小林睦大谷一弘
Owner MITSUBISHI ELECTRIC CORP