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Clock generator for generating accurate and low-jitter clock

A clock generator and clock generation circuit technology, applied in the field of signal transmission, can solve the problem of signal transmission speed limiting the overall performance of the system

Inactive Publication Date: 2004-03-24
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, the speed of signaling between peripherals and the processor / chipset is becoming a major factor limiting overall system performance

Method used

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  • Clock generator for generating accurate and low-jitter clock
  • Clock generator for generating accurate and low-jitter clock
  • Clock generator for generating accurate and low-jitter clock

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] Before describing in detail the preferred embodiment of the clock generator according to the present invention, reference will be made below to figure 1 , a description of prior art clock generators and their associated problems.

[0028] Generally, clock generation for high-speed signal transmission is implemented in two ways. One way is to regenerate the clock according to the received data; since the discrimination between data "0" and "1" is performed using the regenerated clock, this technology is called CDR (Clock and Data Recovery), and the other way ( Although it is a form of CDR technology in a broad sense), the necessary frequency clock is generated inside the chip based on the reference clock provided from outside the chip. Depending on the CDR method, a high frequency reference clock may be required, and CDR techniques may also be employed to generate the clock for this purpose. A transmitter (Tx) for high-speed signal transmission also requires a high-fre...

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PUM

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Abstract

A clock generator has a clock generating circuit, a phase difference detection circuit, and a control signal generating circuit. The clock generating circuit has a function for varying a clock phase in accordance with a control signal. The phase difference detection circuit compares the clock phase output from the clock generating circuit with a phase of a reference waveform, and detects a phase difference therebetween. The control signal generating circuit generates a control signal for controlling the clock phase of the clock generating circuit, based on phase difference information obtained from the phase difference detection circuit. The phase difference detection circuit has a plurality of phase detection units. At least one of the plurality of phase detection units carries out a direct phase detection in which a phase of the clock is directly compared with the phase of the reference waveform, and at least the other one of the plurality of phase detection units carries out an indirect phase detection using a phase-synchronized waveform generating circuit generating a waveform synchronized in phase with the reference waveform or an output of the clock generating circuit and a phase information extracting circuit extracting phase information from the phase-synchronized waveform.

Description

technical field [0001] The invention relates to a signal transmission technology capable of realizing high-speed signal transmission between multiple LSI chips or between multiple devices or circuit groups in a single chip, or between multiple boards or cabinets, and specifically relates to a A clock generator for high bit rate signaling. Background technique [0002] Recently, the performance of various components used in computers and other information processing equipment has been greatly improved. In particular, for example, the performance of semiconductor memory devices such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) and other semiconductor devices such as processors and switching LSIs has greatly improved. [0003] The improvement in performance of semiconductor memory devices, processors, etc. has reached a point where system performance cannot be further improved unless the signal transmission speed between components or elements ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/04G06F1/08H03L7/00H03L7/07H03L7/081H03L7/087H03L7/089H03L7/091H03L7/093H04L7/033
CPCH03L7/093H03L7/07H03L7/0812H03L7/091H03L7/087H03L7/0891H04L7/033H03L7/0816H03L7/00
Inventor 田村泰孝
Owner FUJITSU LTD