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Address translation unit performing address translation from virtual address to physical address

A technology of virtual address and address transformation, which is applied in the direction of micro-instruction address formation, micro-control device, memory address/allocation/relocation, etc., and can solve problems such as not reaching sufficient high speed

Inactive Publication Date: 2004-06-02
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For high-speed address conversion requests from virtual addresses to physical addresses, although methods such as reducing the parasitic capacitance of the matching line have been used to achieve high-speed address conversion, in fact, they have not achieved sufficient high speed.

Method used

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  • Address translation unit performing address translation from virtual address to physical address
  • Address translation unit performing address translation from virtual address to physical address
  • Address translation unit performing address translation from virtual address to physical address

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0022] (A-1. Device structure)

[0023] (A-1-1. Overall structure)

[0024] First, referring to FIG. 1, the structure of a translation lookaside buffer (called TLB) 100 according to Embodiment 1 of the present invention will be described.

[0025] As shown in FIG. 1 , the TLB 100 mainly includes a control section 805 for controlling operations, a tag section 806 for holding virtual addresses, a physical address data section 807 for holding virtual addresses held in the tag section 806, and the like.

[0026] Through the virtual address input path 801, a virtual address output by a CPU (not shown) located outside is supplied to the control section 805, and an address space identifier (referred to as ASID) indicating which address space the access corresponds to is held. ) to the ASID register 802 via the ASID input path 803 to supply the ASID. Furthermore, an ASID register change notification signal 101 for notifying the control unit 805 of a change in the contents of the ASI...

Embodiment 2

[0118] (B-1. Device structure)

[0119] Referring to FIG. 5, the structure of TLB 200 according to Embodiment 2 of the present invention will be described. In addition, the same structures as those of the TLB 100 shown in FIG. 1 are denoted by the same symbols, and description thereof will not be repeated.

[0120] As shown in Figure 5, in each mark input part 808 of TLB200, through ASID matching line 401, connect the multiple CAM unit 813 of ASID holding part 810 and the CAM unit 813 of valid bit part 812 in parallel, also compare and judge with ASID simultaneously Portions 102A are connected.

[0121] Also, the plurality of CAM units 813 of the virtual address holding section 811 and the virtual address comparison determination section 104A corresponding to the tag input section 808 including the virtual address holding section 811 are connected by the virtual address matching line 402 .

[0122] Here, the ASID comparison decision section 102A performs a comparison decisio...

Embodiment 3

[0155] (C-1. Device structure)

[0156] (C-1-1. Overall structure)

[0157] Referring to FIG. 6, the structure of the TLB 300 according to Embodiment 3 of the present invention will be described. In addition, the same structures as those of the TLB 100 shown in FIG. 1 are assigned the same symbols, and the description thereof will not be repeated.

[0158] As shown in FIG. 6 , TLB 300 is provided with ASID comparison and determination section 501 instead of ASID comparison and determination section 102 of TLB 100 . A test data control signal 502 (selection control signal) and a test data input signal 503 (external signal) are supplied to the ASID comparison determination section 501 .

[0159] Here, the test data control signal 502 and the test data input signal 503 are, for example, TLB operation test signals supplied from a test circuit provided on the semiconductor chip or a tester outside the chip.

[0160] In the ASID comparison and determination unit 501 , the ASID va...

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Abstract

Provided is a TLB that can translate rapidly a virtual address to a physical address at small power consumption. A tag entry part (808) includes an ASID hold part (810), virtual address hold part (811), valid bit part (812), ASID comparison judgment part (102), and a virtual address comparison judgment part (104). By an ASID match line (105), a plurality of CAM cells (813) of the ASID hold part (810) are connected in parallel to each other and also connected to the ASID comparison judgment part (102). By a virtual address match line (106), a plurality of CAM cells (813) of the virtual address hold part (811) are connected in parallel to each other and also connected to the virtual address comparison judgment part (104). An ASID effective signal (107) is provided from the ASID comparison judgment part (102) to the virtual address comparison judgment part (104).

Description

technical field [0001] The present invention relates to an address conversion device for converting a virtual address into a physical address, and more particularly to a memory management unit (MMU: Memory Management Unit) used in a central processing unit (CPU: Central Processing Unit) that operates a virtual storage system. A translation lookaside buffer (hereinafter referred to as TLB (Translation Lookaside Buffer)) for address translation. Background technique [0002] The CPU operating the virtual storage system outputs virtual storage addresses on the logical storage space when accessing commands and data. However, since the actual commands and data are kept in the physical address in the physical space, the MMU is used to convert from the virtual address to the physical address. At this time, in order to perform address conversion at high speed, a TLB provided in the MMU is used. [0003] As a conventional technology of a semiconductor device using a virtual storage...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F9/26G06F9/34G06F12/00G06F12/02G06F12/04G06F12/10G11C15/04
CPCY02B60/1225G06F2212/1028G06F12/1036Y02D10/00
Inventor 桝井规雄
Owner RENESAS ELECTRONICS CORP
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