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PLL cycle slip detection

A technology of phase-locked loop and phase detector, applied in the field of frequency synthesis based on phase-locked loop, can solve the problem that the phase detector cannot provide linear detection and other problems

Inactive Publication Date: 2004-07-28
TELEFON AB LM ERICSSON (PUBL)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Typically, phase detectors used in PLL circuits cannot provide linearity detection when the phase difference between the two signals is greater than ±2π radians

Method used

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  • PLL cycle slip detection
  • PLL cycle slip detection
  • PLL cycle slip detection

Examples

Experimental program
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Embodiment Construction

[0013] Now look at the attached picture, figure 1 is a diagram of a Phase Locked Loop (PLL), indicated generally at 10 . PLL 10 includes phase / frequency detector (PFD) 12 , control circuit 14 , loop filter 16 , voltage controlled oscillator (VCO) 18 and period slip detector 20 .

[0014] In general, PFD 12 generates PLL control signals based on the phase difference between two input signals. As shown, PFD 12 receives two input signals, an output based on a reference clock (typically a crystal oscillator), and an output signal based on VCO 18 . The PLL 10 is used to make the frequency of the VCO output signal be several times or a fraction of the required output signal of the reference clock. PFD 12 generates PLL control signals output up (OUTPUT UP) and output down (OUTPUT DOWN) for control circuit 14 . The output up and output down signals cause control circuit 14 to adjust the control voltage applied to VCO 18 . The control circuit 14 may be, for example, a charge pump c...

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Abstract

A cycle slip detector interfaces with a phase / frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed +-2pi radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PFD, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Description

Background of the invention [0001] The present invention relates generally to frequency synthesis and, more particularly, to frequency synthesis based on phase locked loops. [0002] Radio frequency (RF) communication devices, such as mobile terminals within a wireless communication system, receive and transmit signals by using precise timing or frequency reference signals. This reference signal is often used to obtain other signals, which may be higher or lower in frequency, but have the inherent stability and precision of a reference signal. This often requires the frequency or timing of one signal to be slaved to the other, or to monitor the phase or frequency difference between the two signals, leading to dedicated circuits such as phase-locked loops (PLLs). [0003] A typical PLL structure has a controllable oscillator that produces an output signal, a detector that produces an error signal based on the phase or frequency difference between a feedback signal derived from...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/089H03L7/199
CPCH03L7/199H03L7/0891
Inventor D·霍莫尔T·琼斯N·克莱默
Owner TELEFON AB LM ERICSSON (PUBL)