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Nonlinear circuit model order-reducing method combining two-side projection with single-side projection

A nonlinear circuit and bilateral projection technology, applied in the field of electronics, can solve the problems of difficult linear system reduction, poor order reduction accuracy, difficult system order, etc.

Inactive Publication Date: 2004-09-15
FUDAN UNIV
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Problems solved by technology

However, the disadvantage of this method is that the accuracy of the order reduction is poor.
[0050] Can see B 2 The number of column vectors is the input z of the linear system (13) 1 z 1 dimension q 1 2 , if the order q of the reduced-order system (11) of subsystem (2) 1 is higher, then enter z 1 z 1 dimension q 1 2 is higher, resulting in B 2 The number of column vectors in is relatively large, then V 2 There are more column vectors in , so use V 2 Transform: x 2 ≈V 2 z 2 The order q of the reduced-order system obtained after reducing the order of the linear system (13) 2 will not be low if V 2 If the number of vectors in is close to the order N of the original system (13), then the order q of the reduced system 2 It is close to the order of the original system, so the reduction of the original system is meaningless
That is, the high-dimensional input z 1 z 1 It makes it difficult to reduce the order of the linear system (13) in the true sense
This situation is more likely to occur in the process of reducing the order of the linear system (4), because when the order of the subsystem (2) is reduced, the input in the subsystem (4) contains z 1 z 1 z 1 , that is, the dimensionality of the input to subsystem (4) is at least q 1 3 , so it is more difficult to ensure that the order of the reduced system is relatively low (see Figure 4 )

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  • Nonlinear circuit model order-reducing method combining two-side projection with single-side projection
  • Nonlinear circuit model order-reducing method combining two-side projection with single-side projection
  • Nonlinear circuit model order-reducing method combining two-side projection with single-side projection

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Embodiment Construction

[0085] The present invention is further illustrated below by specific examples.

[0086] by Figure 1 Take the circuit in as an example, the number of nodes in the circuit is N=100, and the order of the nonlinear circuit model (1) obtained from this circuit is N=100. The input signal is a step signal, see Figure II . To reduce the order of this nonlinear system,

[0087] The first step: first approach the original nonlinear system (1) with the linear system (2) (3) (4).

[0088] The second step: reduce the order of the linear system (2) using the reduction technique of bilateral projection:

[0089] Calculate the matrices V and W first, and select the first 6 right-end moment vectors

[0090] A 1 -1 B,A 1 -2 B,...A 1 -6 B

[0091] and the first 6 left end moment vectors

[0092] C,A 1 -1 C,A 1 -2 C,...,A 1 -5 C,...

[0093] Biorthogonalize the two sets of vectors. Biorthogonal technology is realized by using the existing algorithm La...

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Abstract

Model reduction technique is a kind of very effective technique for raising speed of simulating circuit in order to improve scheme of designing circuit in due course. In the invented method, reduced order is carried out for non-linear circuit model, that is to say bilateral projection reduction is adopted for first order sublinear system of non-linear system; unilateral projection reduction is adopted for second, third and fourth order sublinear systems. The invention makes non-linear circuit model reduce to lower order, but keeps higher accuracy.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a model reduction method for nonlinear circuits. technical background [0002] Integrated circuits have been developed to the point where electronic systems containing more than 1 billion devices can be integrated on a single chip, that is, System on One Chip (SOC). For millions of large-scale circuits, how to quickly and accurately simulate and verify the correctness of its design within a reasonable time has become a bottleneck in the design of system-on-chip (SOC). According to statistics, the time for SOC chip simulation verification has accounted for 70% of the entire design time. [0003] At present, more and more SOC chips are digital-analog hybrid. In the design of analog integrated circuits and digital-analog hybrid circuits, because most of the analog circuits are nonlinear circuits, the time spent on transient, steady-state and spectrum analysis is se...

Claims

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Application Information

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IPC IPC(8): G06F17/50H01L21/66H01L21/82H01L27/00
Inventor 曾璇冯丽红
Owner FUDAN UNIV