Semiconductor memory device

Abstract

Each memory block of a memory device a plurality of memory cells connected to a plurality of bit line pairs, a column selecting circuit, and a pre-charge and write control circuit. The column selecting circuit includes a plurality of CMOS transmission gates, each CMOS transmission gate including an NMOS transistor connected between one bit line of a bit line pair and a sense bit line of a sense bit line pair, and a PMOS transistor connected between the one bit line and one of the write bit lines of a write bit line pair. During a write operation, only the NMOS transistor of a selected one of the CMOS transmission gates is turned on, and the PMOS transistor of the selected CMOS transmission gate and the PMOS and NMOS transistors of all of the CMOS transmission gates except the selected one are all turned off.

Description

[0001] This application claims priority from Korean Patent Application No. 2003-11492 filed on February 24, 2003, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates to a semiconductor storage device, more particularly, to a semiconductor storage device embedded in a system-on-chip (SOC, system-on-chip). Background technique [0003] Operations of a semiconductor memory device embedded in a conventional system-on-chip (SOC) include a precharge operation, a write operation, and a read operation. The precharge operation precharges bit line pairs and sense bit line pairs to a precharge voltage level in response to a precharge enable signal prior to write and read operations. The write operation writes data into the selected memory cell through the write bit line pair and the bit line pair in response to the write enable signal. The read operation reads data stored in the selected memory cell throug...

AI Technical Summary

Problems solved by technology

Therefore, conventional semiconductor devices have a problem of increased power consumption during write operations

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