Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for decreasing operating frequency of virtual cascade restoring module

A technology of working frequency and virtual concatenation, applied in the field of digital transmission, can solve the problems of chip design, verification and the difficulty of back-end work, so as to reduce the difficulty and facilitate processing.

Inactive Publication Date: 2005-01-26
ZTE CORP
View PDF0 Cites 14 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is the disadvantages of the existing technology that the chip design, verification and back-end work are difficult due to the high frequency of the virtual cascade recovery clock, in order to provide a method that can reduce the working frequency of the virtual cascade recovery module. Frequency, reduce the maximum operating frequency inside the chip and the data frequency of the interface with the external RAM, thereby reducing the difficulty of chip development

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for decreasing operating frequency of virtual cascade restoring module
  • Method for decreasing operating frequency of virtual cascade restoring module
  • Method for decreasing operating frequency of virtual cascade restoring module

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] The method of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0030] figure 1 It is a schematic diagram of the relationship between the bit width conversion module and the virtual concatenation recovery module. What the present invention introduces are two modules with shadows in the figure. The 8-8xN module is located between the interface of the SDH and the virtual concatenation recovery module, and the 8xN-8 module is between the virtual concatenation recovery and the downstream module.

[0031] figure 2 It is the functional block diagram of the 8-8xN merging process. The 8-bit wide data data is cached for the first time to get data b1, after the second cache to get data b2, and after the Nth cache to get data bN, the N The 8-bit wide data is combined into 8xN-bit wide data in sequence, and the data frequency is the same as before conversion, and sent to Figure 4 shown in the storage device handle.

[00...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a method which can reduce working frequency of the virtual cascade connection resume module. The data bus frequency is reduced through changing the bit wide of the data. It includes: first, at the interface of the virtual cascade connection resume module and the SDH transaction, the byte format of the SDH data is changed into 8xN ( the N equals to two, three, four, five, and so on ) bit format, and the other corresponding indication signal is changed; second, the 8xN bit data is transmitted to the virtual cascade connection resume module; third, the 8xN bit data sent out after the disposing of the virtual cascade connection resume module is changed into 8 bit data, and the corresponding indication signal is changed. The invention can reduce the highest working frequency in the chip and the data frequency at the outer RAM interface, thus, the exploitation difficulty of the chip is reduced. Moreover, at mapping path of the two poles pointer, the high-order pointer is adjusted to low-order pointer, this can further simplify the transaction of the virtual cascade connection resume.

Description

technical field [0001] The invention relates to the field of digital transmission, in particular to a virtual concatenation recovery method in an SDH (Synchronous digital hierarchy, ie synchronous digital hierarchy) system. Background technique [0002] In the SDH system, in order to flexibly network and improve bandwidth utilization efficiency, virtual concatenation technology has increasingly become the main method of data transmission. The principle is to allow any number of small containers to be cascaded and assembled into a relatively large container. Data transmission business. This technology can cascade containers of different rates such as VC-11, VC-12, VC-3, VC-4, etc., allowing very fine-grained bandwidth adjustment and providing more accurate bandwidth than adjacent cascading. In addition, since the services of virtual concatenation are regarded as multiple independent containers (that is, non-concatenated containers) in the network, they can be transmitted thr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/08H04L29/10
Inventor 周炼
Owner ZTE CORP