Memory device
A technology for storage devices and storage units, which is applied in static memory, digital memory information, information storage, etc., and can solve the problem that the size of the layout area has a great influence
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no. 1 example
[0054] image 3 is a cross-sectional view showing the structure of a memory cell of the memory device according to the first embodiment of the present invention. Figure 4A is shown image 3 the floor plan of the storage unit, and Figure 4B is shown image 3 Schematic diagram of the layout of the storage unit. Figure 5A is shown image 3 A graph of the voltage-current characteristic curve between the source and the drain in a field effect transistor used as a memory cell in , and Figure 5B is shown image 3 Schematic diagram of the operation of the latch circuit of the memory cell.
[0055] like image 3 As shown, the memory cell of the memory device in the first embodiment includes a field effect transistor 104 , a field effect transistor 105 , a cell capacitor 106 and a resistance device 107 . Field effect transistor 104 is formed on substrate 103 . The field effect transistor 105 is provided adjacent to the field effect transistor 104 , and the channel region of...
no. 2 example
[0074] Image 6 is a cross-sectional view showing a memory device according to a second embodiment of the present invention for two memory cells. Figure 7 is shown Image 6 Schematic layout of the memory cell shown in .
[0075] like Image 6 As shown, each of the memory cells 1 and 2 serving as memory cells of the memory device in the second embodiment includes a field effect transistor 204 , a field effect transistor 205 , a cell capacitor 206 and a resistance device 207 . Field effect transistor 204 is formed on substrate 203 . Field effect transistor 205 is formed on field effect transistor 204 through insulating layer 216 . A resistive device 207 is formed on the source region 205S of the field effect transistor 205 to contact the source region 205S at one end. The gate 204G of the field effect transistor 204 is connected to the word line 202 , its source region 204S is connected to the bit line 201 , and its drain region 204D is connected to the source region 205S ...
no. 3 example
[0080] Figure 8 is a cross-sectional view showing a memory cell of a memory device according to a third embodiment of the present invention. Figure 9A is shown Figure 8 the floor plan of the storage unit, and Figure 9B is shown Figure 8 Schematic diagram of the layout of the storage unit. Figure 8 is shown along the Figure 9A The line B-B looks at the cross-sectional view of the memory device.
[0081] like Figure 8 As shown, similar to the first embodiment, the memory cell of the memory device in the third embodiment includes a field effect transistor 304 , a field effect transistor 305 , a cell capacitor 306 and a resistance device 307 . Field effect transistor 304 is formed on substrate 303 . Field effect transistor 305 is provided adjacent to field effect transistor 304 and the channel region electrically isolates substrate 303 . A resistive device 307 is formed on the source region 305S of the field effect transistor 305 to be connected to the source regio...
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