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Frequency divider

A frequency and register technology, applied in instruments, pulse counters, generating/distributing signals, etc., can solve problems such as shortening chip life and damaging state values

Inactive Publication Date: 2005-05-25
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The unexpected voltage overshoot or undershoot described above may damage the state value stored in the memory unit of the chip or may shorten the life of the chip

Method used

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  • Frequency divider
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Examples

Experimental program
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Embodiment Construction

[0023] Referring now to FIG. 1, a block diagram of one embodiment of a computer system is shown. The computer system includes a processor 100 connected to a system controller 120 via a system bus 110 . The system controller 120 is connected to the main memory 130 through a memory bus 135 . System controller 120 is also connected to graphics adapter 140 via graphics bus 145 . The peripheral controller 150 is connected to the system controller 120 through a peripheral bus A155. Different peripheral devices such as 160A and 160B can be connected to peripheral bus A 155 and peripheral bus B 165 respectively. In one embodiment, the system controller 120 may be a Northbridge integrated circuit, which may be part of a chipset used with the processor 100 . In addition, the system controller 120 may be integrated with the processor 100 . In such an integrated embodiment, main memory 130 may be directly connected to processor 100 . In the illustrated embodiment, the processor 100 i...

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PUM

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Abstract

The present invention provides a method and mechanism for generating a clock signal with relatively linear increase and decrease in clock frequency. A first clock signal having a first frequency is generated and then a second clock signal having a second frequency is generated using the first frequency. The second clock signal is generated by subtracting selected pulses from the first clock signal. The specific bit pattern is stored in the storage element. The bits are then selected and transferred from the storage element at a frequency determined by the first clock signal. The transmitted bits are used to construct the second clock signal. By selecting a particular pattern of bits that are selected and transmitted, the frequency of the second clock signal can be determined. Furthermore, by changing the pattern of bits on the register at selected points in time, the frequency of the second clock signal can be changed in a relatively linear manner.

Description

technical field [0001] The present invention relates to power management of computer systems, and more particularly to controlled entry and exit of low power consumption states. Background technique [0002] As computer systems become more and more powerful, power management has gradually become a very important part of the overall computer system design. This is especially noticeable for portable applications. In order to reduce the power consumption of computer systems, many computer systems employ processors that can enter a standby or low power consumption mode after a specified period of inactivity. In addition, the same low power mode can also be applied in the chipset paired with the processor to further reduce the power consumption caused by the system. [0003] There are many ways to put computer system components into low power modes. For integrated circuits using complementary metal-oxide-semiconductor (CMOS) technology, the transition from logic 1 to logic 0 a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05B41/282G06F1/08H05B37/02
CPCG06F1/08H03K23/66G06F1/00
Inventor P·E·马德里D·R·梅耶尔
Owner ADVANCED MICRO DEVICES INC