Improved method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array

Abstract

A method of storing a data pattern and reproducing the data pattern within an array 30 of memory cells 48, which includes active columns 45b and 45g and inactive columns 46c and 45f, comprises storing the data pattern within the active columns 45b and 45g. An inactive memory cell programming pattern 32 is identified. The inactive memory cell programming pattern 32 identifies all, or a selected plurality, of the memory cells 48 in the inactive columns 45c and 45f in which a charge is to be stored for the purpose of periodically storing a charge in such memory cells 48 to prevent over erasure, during bulk erase, and leakage to active memory cells 48.

Description

technical field [0001] The present invention relates generally to flash memory cell devices, and more particularly to improvements in systems and methods for reading charge previously stored in a column of charge trapping dielectric flash memory cells adjacent to a passive column. Background technique [0002] The traditional floating gate flash memory type electrically erasable programmable read-only memory (EEPROM) uses a memory cell (memory cell), which is characterized in that it is located on a crystalline silicon substrate and has a tunnel oxide (SiO 2 ), a polysilicon floating gate on the tunnel oxide, an interlayer dielectric (typically an oxide, nitride, or oxide stack) on the floating gate, and a control gate on the interlayer dielectric vertical stack. Within the substrate are a channel region underlying the vertical stack, and source and drain diffusion regions at opposite ends of the channel region. [0003] Floating gate flash memory cells are programmed by i...

AI Technical Summary

Problems solved by technology

Multiple consecutive erase cycles cause depletion of the charge storage region, thereby lowering the threshold voltage of the memory cell, even in its erased (unprogrammed) state

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