Manufacturing method of integrated circuit and its structure
A manufacturing method and integrated circuit technology, applied to a method and the obtained structure field, can solve problems such as gate oxide layer leakage, leakage production cost, serious leakage, etc., and achieve reduction of leakage problems, high voltage, and improved The effect of pressure resistance
Active Publication Date: 2006-03-29
MOSEL VITELIC INC
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Problems solved by technology
The above two etchings, and the cleaning in the acid bath after etching, will make the corner oxide layer 121 above the trench susceptible to corrosion by ions and hydrofluoric acid (HF), resulting in leakage of the gate oxide layer.
In addition, when the gate oxide layer is thinned in order to meet the electrical requirements, it will inevitably make the leakage situation more serious
[0005] Due to the existing technology or knowledge, an ESD protection circuit is added after the power device MOS is manufactured, which uses two polysilicon layer deposition and etching processes, which can easily cause gate oxide layer leakage, so , the present application provides a method for simultaneously manufacturing trench-type components and planar components and the resulting structure, which can solve the problem of leakage, reduce production costs and improve yield
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[0037] In order to effectively improve the process of depositing and etching the polysilicon layer twice in the prior art, as well as the leakage problem of the gate oxide layer easily caused by this existing process, this application proposes a novel integrated circuit manufacturing method and structure to Solve the above problems.
[0038] According to an embodiment of the present application, the manufacturing method of the integrated circuit of the present application can be described by the flow shown in FIGS. 2( a ) to ( e ).
[0039] Please refer to Fig. 2 (a), there is trench 24 on the semiconductor material of polysilicon epi, on the surface of semiconductor material is oxide layer 22, and undoped polysilicon layer 23 is deposited on oxide layer 22, and this polysilicon layer 23 is divided into trenches The polysilicon layer 231 in the ditch area 25 and the polysilicon layer 233 in the planar area 26, wherein the ditch area 25 is further divided into a cell area 251 (...
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The invention is a making method and structure for integrated circuit (IC). It makes primary polycrystalline sedimentation and etching to form the grid of a channel element and the polycrystalline layer of a planar element. The method and structure overcomes the leakage problem of grid oxide layer and effectively improves voltage proofing performance, reduces production cost and raises the yield. The invention has outstanding technical characteristic in the technical field of power element.
Description
technical field [0001] The present application relates to a manufacturing method and structure of an integrated circuit, in particular to a method for simultaneously manufacturing trench elements and planar elements and the obtained structure. Background technique [0002] The metal oxide field effect transistor (MOSFET, MOS) of the power element has high input impedance (inputimpedance), so it is particularly vulnerable to damage by electrostatic discharge pulse (ESD pulse). In addition, in order to obtain a MOS with a lower threshold voltage (Vt) in the current integrated circuit manufacturing process, the thickness of the gate oxide layer (gate oxide) needs to be thinner. Under such requirements, as long as the If a voltage of about 15-20V is used in the process, the gate oxide layer will be easily damaged, which will cause leakage and other situations. Therefore, it is necessary to add an electrostatic discharge (ESD) protection circuit in the application of the power e...
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Login to View More IPC IPC(8): H01L21/82H01L27/02
Inventor 谢兴煌张建平曾茂松袁天民
Owner MOSEL VITELIC INC