Etching method and method for manufacturing thin film transistor employing the same

Abstract

This invention relates to one film transistor process method, which comprises the following steps: First forming grating electrode on baseboard; Then forming isolation layer on the baseboard covered with grating electrode; Then forming semiconductor layer on the isolation layer; Then forming ohm contact layer on the semi-conductor layer with material of n+ mixture crystal silicon; Then forming channel by semi-conductor layer and ohm contact layer above electrode; Then forming source electrode or leakage electrode on the both sides of channel; Then converting ohm contact layer uncovered source or leakage electrodes surface layer into earth silicon; Then removing ohm contact layer part.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor element, and in particular relates to an etching method and a manufacturing method of a thin film transistor using the etching method. Background technique [0002] The rapid progress of the multimedia society is mostly due to the rapid progress of semiconductor components or man-machine display devices. As far as the display is concerned, the cathode ray tube (Cathode Ray Tube, CRT) has been monopolizing the display market in recent years because of its excellent display quality and economical efficiency. However, for the environment where individuals operate multiple terminals / display devices on the table, or from the perspective of environmental protection, if the trend of energy saving is predicted, there are still many problems in the space utilization and energy consumption of cathode ray tubes. However, there is no effective solution to the requirements of lightness, thi...

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Problems solved by technology

However, when performing dry etching on the ohmic contact layer 140, since the material of the ohmic contact layer 140 located around the channel 150 is silicon dioxide, and the material of other parts of the ohmic contact layer 140 is n+ doped amorphous silicon, therefore The ohmic contact layer 140 located around the channel 150 will remain because the etching rate is slower than that of n+ doped amorphous silicon

[0009] In this way, in Figure 1E The region not shown crosses the source / drain 160 around the channel 150, and will be conducted with each other due to the remaining ohmic contact layer 140, resulting in abnormal display of the liquid crystal display

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