Thin film transistor and producing method thereof

Abstract

This invention relates to film transistor, which comprises the following parts: one grating electrode on one baseboard; one grating isolation layer covering grating electrode; one non-crystal silicon area formed on isolation layer on grating electrode; one mixing non-crystal silicon area formed on the area; one source electrode metal area and one leakage metal area formed on mixture non-crystal silicon area and the source metal area and leakage electrode are separate; one protective layer formed on grating isolation layer covering source metal area, leakage metal area and data line metal area with first, second and third medium holes exposed on leakage metal area, source metal area and data line metal area partial surface; one conductive layer formed on protective layer covering first, second and third medium holes and connecting data line meta area and source electrode metal area.

Description

technical field [0001] The invention relates to a thin film transistor and a manufacturing method thereof, in particular to a thin film transistor capable of reducing leakage current and a manufacturing method thereof. Background technique [0002] Active matrix TFT-LCD (AMLCD) has gradually replaced the traditional CRT display due to its advantages such as lightness and thinness, and the demand for AMLCD's size and display quality is also increasing day by day. As the resolution of the display increases, the number of scan lines also increases, and under the same frame time, the time for each gate scan line to be selected is also shortened, so for transistors The requirements for the switching characteristics are becoming more and more stringent. Taking a thin film transistor (TFT) as an example, when the TFT is turned off, excessive leakage current cannot be generated. [0003] Generally, when manufacturing a thin film transistor, the amorphous silicon (a-Si) layer in the...

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Problems solved by technology

However, the source metal region 151 and the drain metal region 152 will be in contact with the sidewalls of the island structure (i.e. the amorphous silicon layer 13 and the doped amorphous silicon layer 14), as figure 1 As shown by the dotted line in , a Schottky contact is formed to generate a leakage path

When the gate 11 receives a negative bias and the drain metal region 152 receives a positive bias, the leakage current of the TFT 1 will increase, thereby affecting the switching characteristics.

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