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Semiconductor device

A technology for semiconductors and devices, applied in the field of semiconductor devices, can solve the problems of insufficient reliability, decreased reliability, filling and sealing resin, etc., to eliminate adverse effects, improve processing accuracy and processing time, and reduce thickness. Effect

Inactive Publication Date: 2006-08-16
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the case of actually providing a spot facing portion, it is difficult to implement forming
If the back surface of the semiconductor chip is machined with a dicing blade to reduce the thickness of the semiconductor chip, there is a problem of lowered reliability due to damage to the wafer (chip) by the dicing blade in the grinding method
In addition, mass production is difficult in terms of processing accuracy and time required for processing
[0008] Furthermore, in the case of applying Patent Document 2, even if the chip is to be sealed with the sealing resin, it is difficult to uniformly fill the sealing resin in the spot-faced portion
In particular, it is also apparent that there is such a problem that it is difficult for the sealing resin to reach the rectangular portion on the four corners in the spot facing portion and sufficient reliability cannot be obtained in terms of mechanical strength and sealing characteristics.

Method used

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  • Semiconductor device
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Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0054] A first embodiment of the present invention will be described below with reference to the drawings. figure 1 (a) is a view showing the semiconductor device according to the first embodiment of the present invention when viewed from above, figure 1 (b) is a cross-sectional view taken along A-B thereof.

[0055] figure 2 The state before resin sealing is shown. The semiconductor device according to this embodiment is characterized in that the first semiconductor chip 1 as the first semiconductor substrate is accommodated in a recess formed on the surface of the second semiconductor chip 2 as the second semiconductor substrate by anisotropic etching Spotfacing portion (spotfacing portion)) 10. 8 represents underfill, and 9 represents sealing resin.

[0056] The first semiconductor chip 1 and the second semiconductor chip 2 constitute a circuit forming surface on a surface facing away from a bonding surface, and the second semiconductor chip 2 is connected from the c...

no. 2 example

[0073] A second embodiment of the present invention will be described below with reference to the drawings. Figure 5 (a) is a view showing the semiconductor device according to the second embodiment of the present invention when viewed from above, Figure 5 (b) is along Figure 5 (a) Cross-sectional view taken from A-B. The same elements as those of the first embodiment have the same reference numerals and descriptions thereof will be omitted.

[0074] The second embodiment differs from the first embodiment in that a trench portion 11 is provided near the second semiconductor chip 2 to form a passage for sealing resin in such a manner that resin sealing can be easily performed. The groove portions 11 are uniformly provided on each side of the second semiconductor chip 2 and perpendicular to each side so that the sealing resin 5 enters through the groove portions 11 so that the sealing resin 5 can be uniformly filled to eliminate unfilled positions.

[0075] The groove port...

no. 3 example

[0087] Although an example in which wire bonding is used has been described, the second semiconductor chip 2 may be directly connected to the interposer 3 to be drawn out.

[0088] This example is shown in Figure 13 (a) and (b). More specifically, the second semiconductor chip 2 is brought out on the interposer side and direct bonding to the interposer 3 is performed via the bumps 6 .

[0089] The outside can undergo resin sealing or can hold a bare chip. Therefore, a large reduction in size can be achieved.

[0090] Furthermore, in this case, it is also possible to perform bonding and bump formation on the wafer level and then perform dicing for separation into individual semiconductor chips. Therefore, it can be manufactured very easily.

[0091] In addition, the circuit-formed surface of the second semiconductor chip 2 may be placed on the first semiconductor chip 1 side, and connection may be made in the spot-faced portion by direct bonding. In this case, the second ...

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PUM

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Abstract

In an SiP constituted by laminating a plurality of chips, it is an object to reduce a thickness of the SiP without damaging a strength of a chip on an upper side and deteriorating a reliability due to dicing in the case in which the chip on the upper side is larger than a chip on a lower side. A spot facing portion is provided by etching in the vicinity of a center of a bottom face of a chip on an upper side having a circuit formation surface to be a top face, and a chip on a lower side is disposed on an inside of the spot facing portion.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to SiP (System in Package) technology for mounting a plurality of chips on the same package to constitute a semiconductor device while maintaining strength and reducing thickness and downsizing to almost chip size. Background technique [0002] As the density of semiconductor devices on printed circuit boards has increased, the size of semiconductor devices has been reduced. In recent years, a semiconductor device having a size reduced to almost the size of a chip has been developed. In order to meet the demand for size reduction, SiP (System in Package) technology for mounting a system as one package has been proposed. [0003] As a technique for realizing SiP, the publication number is JP-A-11-204720 (see image 3 ) proposes a semiconductor device in which another semiconductor chip is stacked on a surface facing down on the opposite side of the circuit forming surface of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L25/065H01L23/488
CPCH01L2924/10158H01L25/0657H01L2225/06586H01L2224/73204H01L24/32H01L2224/16H01L2224/48227H01L2225/06517H01L2924/01005H01L2924/01033H01L2224/32145H01L2924/01006H01L2924/15311H01L2225/0651H01L2225/06555H01L2224/16225H01L2224/48091H01L25/0652H01L2224/73265H01L2225/06562H01L2224/32225H01L24/73H01L2924/00011H01L2924/00014H01L2924/00H01L2924/00012H01L2224/0401
Inventor 德永真也
Owner PANASONIC CORP