Vertical pnp transistor and method of making same

Abstract

The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.

Description

technical field [0001] The present invention relates to device structures including high performance vertical PNP and NPN transistors and methods of fabrication thereof. Background technique [0002] The gradual increase of mobile communication has promoted the development of radio frequency (RF) communication. In particular, an increase in the market requires lower power consumption and higher performance. One possible solution for many applications that have been found is bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. See, for example, Chyan et al., "A 50 GHz 0.25 µm... BiCMOS Technology for Low-Power Wireless-Communication VLSI's," BCTM, 1998, p. 128. [0003] However, because only high-performance vertical NPN transistors are commonly available, many BiCMOS circuit designs are limited by speed, power consumption, and noise. Low-performance lateral PNP transistors are available with cut-off frequencies less than 1 GHz (f T ) and cannot be used wi...

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Problems solved by technology

[0004] Furthermore, it is expensive to integrate PNP transistors in conventional BiCMOS processes designed only to form complementary metal-oxide-semiconductor (CMOS) devices and NPN bipolar devices

Additional process steps are usually required to form PNP transistors, which results in longer process times and increased manufacturing costs

Thus, there is also a need for a method for integrating PNP transistor process steps into a conventional BiCMOS process with few or no additional process steps

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